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Restore old ffY behaviour

This commit is contained in:
Eddie Hung 2019-07-19 22:47:08 -07:00
parent f9d08a5e5e
commit e0720a8018
1 changed files with 5 additions and 16 deletions
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21
passes/pmgen/ice40_dsp.pmg
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@ -3,7 +3,6 @@ pattern ice40_dsp
state <SigBit> clock state <SigBit> clock
state <bool> clock_pol state <bool> clock_pol
state <SigSpec> sigA sigB sigY sigS state <SigSpec> sigA sigB sigY sigS
state <SigSpec> sigYused
state <Cell*> addAB muxAB state <Cell*> addAB muxAB
match mul match mul
@ -54,28 +53,18 @@ code sigB clock clock_pol
} }
endcode endcode
// Extract the bits of Y that actually have a consumer
// (as opposed to being a sign extension)
code sigY sigYused
sigY = port(mul, \Y);
int i;
for (i = GetSize(sigY); i > 0; i--)
if (nusers(sigY[i-1]) > 1)
break;
sigYused = sigY.extract(0, i);
endcode
match ffY match ffY
select ffY->type.in($dff) select ffY->type.in($dff)
select nusers(port(ffY, \D)) == 2 select nusers(port(ffY, \D)) == 2
filter param(ffY, \WIDTH).as_int() >= GetSize(sigYused) index <SigSpec> port(ffY, \D) === port(mul, \Y)
filter includes(port(ffY, \D).to_sigbit_set(), sigYused.to_sigbit_set())
optional optional
endmatch endmatch
code clock clock_pol sigY code sigY clock clock_pol
sigY = port(mul, \Y);
if (ffY) { if (ffY) {
sigY.replace(port(ffY, \D), port(ffY, \Q)); sigY = port(ffY, \Q);
SigBit c = port(ffY, \CLK).as_bit(); SigBit c = port(ffY, \CLK).as_bit();
bool cp = param(ffY, \CLK_POLARITY).as_bool(); bool cp = param(ffY, \CLK_POLARITY).as_bool();