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Merge pull request #1679 from thasti/delay-parsing 

Fix crash on wire declaration with delay
This commit is contained in:
N. Engelhardt 2020-02-13 12:01:27 +01:00 committed by GitHub
parent c244b27b6d 90c78f1f85
commit e069259a53
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 7 additions and 2 deletions
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4
frontends/verilog/verilog_parser.y
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@ -476,7 +476,7 @@ wire_type:
astbuf3 = new AstNode(AST_WIRE); astbuf3 = new AstNode(AST_WIRE);
current_wire_rand = false; current_wire_rand = false;
current_wire_const = false; current_wire_const = false;
} wire_type_token_list delay { } wire_type_token_list {
$$ = astbuf3; $$ = astbuf3;
}; };
@ -1240,7 +1240,7 @@ wire_decl:
} }
if (astbuf2 && astbuf2->children.size() != 2) if (astbuf2 && astbuf2->children.size() != 2)
frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]"); frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
} wire_name_list { } delay wire_name_list {
delete astbuf1; delete astbuf1;
if (astbuf2 != NULL) if (astbuf2 != NULL)
delete astbuf2; delete astbuf2;

5
tests/various/bug1614.ys Normal file
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@ -0,0 +1,5 @@
read_verilog <<EOT
module testcase;
wire [3:0] #1 a = 4'b0000;
endmodule
EOT