mirror of https://github.com/YosysHQ/yosys.git
More opt_const -mux_bool features
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@ -244,20 +244,59 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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}
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}
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if (mux_bool && cell->type == "$mux" && cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) {
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if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
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cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) {
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replace_cell(module, cell, "mux_bool", "\\Y", cell->connections["\\S"]);
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replace_cell(module, cell, "mux_bool", "\\Y", cell->connections["\\S"]);
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goto next_cell;
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goto next_cell;
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}
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}
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if (mux_bool && cell->type == "$mux" && cell->connections["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections["\\B"] == RTLIL::SigSpec(0, 1)) {
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if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
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cell->connections["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections["\\B"] == RTLIL::SigSpec(0, 1)) {
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cell->connections["\\A"] = cell->connections["\\S"];
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cell->connections["\\A"] = cell->connections["\\S"];
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cell->connections.erase("\\B");
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cell->connections.erase("\\B");
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cell->connections.erase("\\S");
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cell->connections.erase("\\S");
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if (cell->type == "$mux") {
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cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\A_SIGNED"] = 0;
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cell->parameters["\\A_SIGNED"] = 0;
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cell->parameters.erase("\\WIDTH");
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cell->parameters.erase("\\WIDTH");
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cell->type = "$not";
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cell->type = "$not";
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} else
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cell->type = "$_INV_";
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did_something = true;
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goto next_cell;
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}
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if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\A"] == RTLIL::SigSpec(0, 1)) {
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cell->connections["\\A"] = cell->connections["\\S"];
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cell->connections.erase("\\S");
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if (cell->type == "$mux") {
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cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\A_SIGNED"] = 0;
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cell->parameters["\\B_SIGNED"] = 0;
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cell->parameters.erase("\\WIDTH");
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cell->type = "$and";
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} else
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cell->type = "$_AND_";
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did_something = true;
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goto next_cell;
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}
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if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) {
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cell->connections["\\B"] = cell->connections["\\S"];
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cell->connections.erase("\\S");
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if (cell->type == "$mux") {
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cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
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cell->parameters["\\A_SIGNED"] = 0;
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cell->parameters["\\B_SIGNED"] = 0;
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cell->parameters.erase("\\WIDTH");
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cell->type = "$or";
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} else
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cell->type = "$_or_";
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did_something = true;
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did_something = true;
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goto next_cell;
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goto next_cell;
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}
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}
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