riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Detect and reject cases that do not map well to iCE40 DSPs (yet) 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-02-20 11:18:19 +01:00
parent 62493c91b2
commit dca65d83a0
2 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
passes/pmgen/ice40_dsp.cc
View File

@ -59,10 +59,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
return; return;
} }
log(" replacing $mul with SB_MAC16 cell.\n");
bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool(); bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool();
if (mul_signed) {
log(" inference of signed iCE40 DSP arithmetic is currently not supported.\n");
return;
}
log(" replacing $mul with SB_MAC16 cell.\n");
Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16"); Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
pm.module->swap_names(cell, pm.st.mul); pm.module->swap_names(cell, pm.st.mul);

10
passes/pmgen/ice40_dsp.pmg
View File

@ -100,6 +100,16 @@ code addAB sigS
addAB = addB; addAB = addB;
sigS = port(addB, \A); sigS = port(addB, \A);
} }
if (addAB) {
int natural_mul_width = GetSize(sigA) + GetSize(sigB);
int actual_mul_width = GetSize(sigY);
int actual_acc_width = GetSize(sigS);
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject;
if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
reject;
}
endcode endcode
match muxA match muxA