diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 7463d598f..8c50a9393 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -59,10 +59,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		return;
 	}
 
-	log("  replacing $mul with SB_MAC16 cell.\n");
-
 	bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool();
 
+	if (mul_signed) {
+		log("  inference of signed iCE40 DSP arithmetic is currently not supported.\n");
+		return;
+	}
+
+	log("  replacing $mul with SB_MAC16 cell.\n");
+
 	Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
 	pm.module->swap_names(cell, pm.st.mul);
 
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 58e1ce0e0..96c62e313 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -100,6 +100,16 @@ code addAB sigS
 		addAB = addB;
 		sigS = port(addB, \A);
 	}
+	if (addAB) {
+		int natural_mul_width = GetSize(sigA) + GetSize(sigB);
+		int actual_mul_width = GetSize(sigY);
+		int actual_acc_width = GetSize(sigS);
+
+		if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
+			reject;
+		if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
+			reject;
+	}
 endcode
 
 match muxA