mirror of https://github.com/YosysHQ/yosys.git
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dc18bf1969
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@ -604,7 +604,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (cell->type.in(ID($xnor), ID($_XNOR_))) {
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cover("opt.opt_expr.const_xnor");
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// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
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int width = cell->getParam(ID::Y_WIDTH).as_int();
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int width = GetSize(cell->getPort(ID::Y));
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replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width));
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goto next_cell;
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}
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@ -0,0 +1,14 @@
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read_verilog -icells << EOT
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module top(...);
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input A;
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output Y;
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$_XNOR_ x (.A(A), .B(A), .Y(Y));
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endmodule
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EOT
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equiv_opt -assert opt_expr
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