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Fix techmap for inout ports connected to inout ports

This commit is contained in:
Clifford Wolf 2017-02-13 16:55:25 +01:00
parent 76c4ee096b
commit db7314bc02
1 changed files with 7 additions and 2 deletions
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9
passes/techmap/techmap.cc
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@ -305,10 +305,15 @@ struct TechmapWorker
// approach that yields nicer outputs:
// replace internal wires that are connected to external wires
if (w->port_output)
if (w->port_output && !w->port_input) {
port_signal_map.add(c.second, c.first);
else
} else
if (!w->port_output && w->port_input) {
port_signal_map.add(c.first, c.second);
} else {
module->connect(c);
extra_connect = SigSig();
}
for (auto &attr : w->attributes) {
if (attr.first == "\\src")