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ice40_dsp: fix typo

This commit is contained in:
Eddie Hung 2020-01-17 16:08:04 -08:00
parent e17f3f8c63
commit db68e4c2a7
2 changed files with 13 additions and 2 deletions
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4
passes/pmgen/ice40_dsp.cc
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@ -73,11 +73,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
// SB_MAC16 Input Interface
SigSpec A = st.sigA;
A.extend_u0(16, st.mul->connections_.at(ID(A_SIGNED), State::S0).as_bool());
A.extend_u0(16, st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
log_assert(GetSize(A) == 16);
SigSpec B = st.sigB;
B.extend_u0(16, st.mul->connections_.at(ID(B_SIGNED), State::S0).as_bool());
B.extend_u0(16, st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
log_assert(GetSize(B) == 16);
SigSpec CD = st.sigCD;

11
tests/arch/xilinx/xilinx_dsp.ys Normal file
View File

@ -0,0 +1,11 @@
read_verilog <<EOT
module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5);
DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1));
assign o2 = a * 16'd0;
wire [42:0] o3, o4;
DSP48E1 m2 (.A(a), .B(b), .P(o3));
assign o4 = a * b;
DSP48E1 m3 (.A(a), .B(b), .P(o5));
endmodule
EOT
xilinx_dsp