changed file() to open() in python scripts

tests/bram/generate.py

@@ -250,10 +250,10 @@ print("Rng seed: %d" % seed)
 random.seed(seed)
 
 for k1 in range(5):
-    dsc_f = file("temp/brams_%02d.txt" % k1, "w")
+    dsc_f = open("temp/brams_%02d.txt" % k1, "w")
-    sim_f = file("temp/brams_%02d.v" % k1, "w")
+    sim_f = open("temp/brams_%02d.v" % k1, "w")
-    ref_f = file("temp/brams_%02d_ref.v" % k1, "w")
+    ref_f = open("temp/brams_%02d_ref.v" % k1, "w")
-    tb_f = file("temp/brams_%02d_tb.v" % k1, "w")
+    tb_f = open("temp/brams_%02d_tb.v" % k1, "w")
 
     for f in [sim_f, ref_f, tb_f]:
         print("`timescale 1 ns / 1 ns", file=f)

tests/fsm/generate.py

@@ -34,7 +34,7 @@ def random_expr(variables):
     raise AssertionError
 
 for idx in range(50):
-    with file('temp/uut_%05d.v' % idx, 'w') as f:
+    with open('temp/uut_%05d.v' % idx, 'w') as f:
         with redirect_stdout(f):
             rst2 = random.choice([False, True])
             if rst2:
@@ -90,7 +90,7 @@ for idx in range(50):
             print('    end')
             print('  end')
             print('endmodule')
-    with file('temp/uut_%05d.ys' % idx, 'w') as f:
+    with open('temp/uut_%05d.ys' % idx, 'w') as f:
         with redirect_stdout(f):
             if test_verific:
                 print('read_verilog temp/uut_%05d.v' % idx)

tests/realmath/generate.py

@@ -40,7 +40,7 @@ def random_expression(depth = 3, maxparam = 0):
     raise
 
 for idx in range(100): 
-    with file('temp/uut_%05d.v' % idx, 'w') as f:
+    with open('temp/uut_%05d.v' % idx, 'w') as f:
         with redirect_stdout(f):
             print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)])))
             for i in range(30):
@@ -56,12 +56,12 @@ for idx in range(100):
             for i in range(100):
                 print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60)))
             print('endmodule')
-    with file('temp/uut_%05d.ys' % idx, 'w') as f:
+    with open('temp/uut_%05d.ys' % idx, 'w') as f:
         with redirect_stdout(f):
             print('read_verilog uut_%05d.v' % idx)
             print('rename uut_%05d uut_%05d_syn' % (idx, idx))
             print('write_verilog uut_%05d_syn.v' % idx)
-    with file('temp/uut_%05d_tb.v' % idx, 'w') as f:
+    with open('temp/uut_%05d_tb.v' % idx, 'w') as f:
         with redirect_stdout(f):
             print('module uut_%05d_tb;\n' % idx)
             print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)])))

tests/share/generate.py

@@ -25,7 +25,7 @@ def maybe_plus_x(expr):
         return expr
 
 for idx in range(100):
-    with file('temp/uut_%05d.v' % idx, 'w') as f:
+    with open('temp/uut_%05d.v' % idx, 'w') as f:
         with redirect_stdout(f):
             if random.choice(['bin', 'uni']) == 'bin':
                 print('module uut_%05d(a, b, c, d, x, s, y);' % (idx))
@@ -60,7 +60,7 @@ for idx in range(100):
                          random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'),
                          random_plus_x() if random.randint(0, 4) == 0 else ''))
                 print('endmodule')
-    with file('temp/uut_%05d.ys' % idx, 'w') as f:
+    with open('temp/uut_%05d.ys' % idx, 'w') as f:
         with redirect_stdout(f):
             print('read_verilog temp/uut_%05d.v' % idx)
             print('proc;;')