riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

abc9_ops: -reintegrate to be sensitive to start_offset too

This commit is contained in:
Eddie Hung 2020-05-02 11:19:04 -07:00
parent 2e78daf1ca
commit da7da44919
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
passes/techmap/abc9_ops.cc
View File

@ -741,8 +741,10 @@ void reintegrate(RTLIL::Module *module)
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
for (auto w : mapped_mod->wires())
module->addWire(remap_name(w->name), GetSize(w));
for (auto w : mapped_mod->wires()) {
auto nw = module->addWire(remap_name(w->name), GetSize(w));
nw->start_offset = w->start_offset;
}
dict<IdString,std::vector<IdString>> box_ports;
@ -989,7 +991,7 @@ void reintegrate(RTLIL::Module *module)
wire->attributes.erase(ID::abc9_scc);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire));
RTLIL::SigSig conn;