From da7da4491901e8c76682b6423658debe160771d9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 2 May 2020 11:19:04 -0700 Subject: [PATCH] abc9_ops: -reintegrate to be sensitive to start_offset too --- passes/techmap/abc9_ops.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 78c902866..1345188a4 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -741,8 +741,10 @@ void reintegrate(RTLIL::Module *module) if (mapped_mod == NULL) log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module)); - for (auto w : mapped_mod->wires()) - module->addWire(remap_name(w->name), GetSize(w)); + for (auto w : mapped_mod->wires()) { + auto nw = module->addWire(remap_name(w->name), GetSize(w)); + nw->start_offset = w->start_offset; + } dict> box_ports; @@ -989,7 +991,7 @@ void reintegrate(RTLIL::Module *module) wire->attributes.erase(ID::abc9_scc); RTLIL::Wire *remap_wire = module->wire(remap_name(port)); - RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire)); + RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); RTLIL::SigSig conn;