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Merge pull request #1571 from YosysHQ/eddie/fix_1570 

mem_arst.v: do not redeclare ANSI port
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Eddie Hung 2019-12-19 12:21:22 -05:00 committed by GitHub
parent 8b2c9f4518 23fcfd0adb
commit d675f22f4e
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1 changed files with 1 additions and 3 deletions
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tests/simple/mem_arst.v
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@ -7,11 +7,9 @@ module MyMem #(
input Clk_i, input Clk_i,
input [AddrWidth-1:0] Addr_i, input [AddrWidth-1:0] Addr_i,
input [DataWidth-1:0] Data_i, input [DataWidth-1:0] Data_i,
output [DataWidth-1:0] Data_o, output reg [DataWidth-1:0] Data_o,
input WR_i); input WR_i);
reg [DataWidth-1:0] Data_o;
localparam Size = 2**AddrWidth; localparam Size = 2**AddrWidth;
(* mem2reg *) (* mem2reg *)