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synth_xilinx: before abc read +/xilinx/cells_box.v

This commit is contained in:
Eddie Hung 2019-04-16 11:21:46 -07:00
parent 3ac4977b70
commit d259e6dc14
1 changed files with 1 additions and 0 deletions
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1
techlibs/xilinx/synth_xilinx.cc
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@ -283,6 +283,7 @@ struct SynthXilinxPass : public Pass
{ {
Pass::call(design, "opt -full"); Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v"); Pass::call(design, "techmap -map +/techmap.v");
Pass::call(design, "read_verilog +/xilinx/cells_box.v");
if (abc == "abc9") if (abc == "abc9")
Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
else else