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fixed typos, build with makefile succeeds

This commit is contained in:
C77874 2024-07-04 09:33:58 -07:00
parent 59e45be275
commit d0cd01adfe
2 changed files with 2 additions and 2 deletions
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2
passes/pmgen/Makefile.inc
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@ -37,7 +37,7 @@ $(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
# -------------------------------------- # --------------------------------------
OBJS += passes/pmgen/microvhip.o OBJS += passes/pmgen/microchip_dsp.o
GENFILES += passes/pmgen/microchip_dsp_pm.h GENFILES += passes/pmgen/microchip_dsp_pm.h
GENFILES += passes/pmgen/microchip_dsp_CREG_pm.h GENFILES += passes/pmgen/microchip_dsp_CREG_pm.h
GENFILES += passes/pmgen/microchip_dsp_cascade_pm.h GENFILES += passes/pmgen/microchip_dsp_cascade_pm.h

2
techlibs/microchip/Makefile.inc
View File

@ -22,7 +22,7 @@ OBJS += techlibs/microchip/microchip_dffopt.o
$(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v)) $(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v)) $(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v)) $(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/pf_dsp_map.v)) $(eval $(call add_share_file,share/microchip,techlibs/microchip/polarfire_dsp_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh)) $(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v)) $(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))