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Merge pull request #1 from alainmarcel/new_peepopts 

Compiles and transforms correctly, fails equiv
This commit is contained in:
Akash Levy 2024-12-17 15:47:53 -08:00 committed by GitHub
parent 0e15edd099 8a6c1005e3
commit cfadf28460
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2 changed files with 11 additions and 8 deletions
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17
passes/pmgen/peepopt_muxadd.pmg
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@ -5,8 +5,8 @@ pattern muxadd
// y = s ? (a + b) : a ===> y = a + (s ? b : 0)
//
state <SigSpec> add_a add_b add_y
state <bool> add_a_signed
state <SigSpec> add_a add_b add_y add_a_ext
state <Const> add_a_signed
state <IdString> add_a_id
match add
@ -21,12 +21,13 @@ match add
set add_a_id A
endmatch
code add_y add_a add_b
code add_y add_a add_b add_a_ext
// Get adder signals
add_a = port(add, \A);
add_b = port(add, \B);
add_y = port(add, \Y);
add_a_ext = SigSpec(add_a);
add_a_ext.extend_u0(GetSize(add_y), param(add, \A_SIGNED).as_bool());
// Fanout of each adder Y bit should be 1 (no bit-split)
if (nusers(add_y) != 2)
reject;
@ -39,7 +40,7 @@ endcode
match mux
// Select mux of form s ? (a + b) : a, allow leading 0s when A_WIDTH != Y_WIDTH
select mux->type == $mux
index <SigSpec> port(mux, \A) === SigSpec({Const(!param(add, \A_SIGNED).bool() ? () : State::S0, GetSize(add_y)-GetSize(add_a)), add_a})
index <SigSpec> port(mux, \A) === add_a_ext
index <SigSpec> port(mux, \B) === add_y
endmatch
@ -55,11 +56,13 @@ code
mux->setPort(\B, add_b);
mux->setPort(\Y, mid);
add->setPort(\B, mid);
add->setPort(\Y, mux_y);
add->setPort(\A, add_a);
add->setPort(\Y, add_y);
module->connect(mux_y, add_y);
// Log, fixup, accept
log("muxadd pattern in %s: mux=%s, add=%s\n", log_id(module), log_id(mux), log_id(add));
add->fixup_parameters();
mux->fixup_parameters();
did_something = true;
accept;
endcode

2
tests/peepopt/muxadd.ys
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@ -13,7 +13,7 @@ module top(a, b, s, y);
endmodule
EOF
check -assert
equiv_opt -assert peepopt
equiv_opt -assert peepopt ;;;
design -load postopt
select -assert-any t:$add %co1 %a w:y %i # assert adder rewired