From 3b7388888c0319cbee402a24cd603a682a881a7d Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 17 Dec 2024 15:33:31 -0800 Subject: [PATCH 1/2] Compiles and transforms correctly, fails equiv --- passes/pmgen/peepopt_muxadd.pmg | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/passes/pmgen/peepopt_muxadd.pmg b/passes/pmgen/peepopt_muxadd.pmg index 856875e3f..137c94d9d 100644 --- a/passes/pmgen/peepopt_muxadd.pmg +++ b/passes/pmgen/peepopt_muxadd.pmg @@ -5,8 +5,8 @@ pattern muxadd // y = s ? (a + b) : a ===> y = a + (s ? b : 0) // -state add_a add_b add_y -state add_a_signed +state add_a add_b add_y add_a_ext +state add_a_signed state add_a_id match add @@ -21,12 +21,13 @@ match add set add_a_id A endmatch -code add_y add_a add_b +code add_y add_a add_b add_a_ext // Get adder signals add_a = port(add, \A); add_b = port(add, \B); add_y = port(add, \Y); - + add_a_ext = SigSpec(add_a); + add_a_ext.extend_u0(GetSize(add_y), param(add, \A_SIGNED).as_bool()); // Fanout of each adder Y bit should be 1 (no bit-split) if (nusers(add_y) != 2) reject; @@ -39,7 +40,7 @@ endcode match mux // Select mux of form s ? (a + b) : a, allow leading 0s when A_WIDTH != Y_WIDTH select mux->type == $mux - index port(mux, \A) === SigSpec({Const(!param(add, \A_SIGNED).bool() ? () : State::S0, GetSize(add_y)-GetSize(add_a)), add_a}) + index port(mux, \A) === add_a_ext index port(mux, \B) === add_y endmatch @@ -55,11 +56,13 @@ code mux->setPort(\B, add_b); mux->setPort(\Y, mid); add->setPort(\B, mid); - add->setPort(\Y, mux_y); - + add->setPort(\A, add_a); + add->setPort(\Y, add_y); + module->connect(mux_y, add_y); // Log, fixup, accept log("muxadd pattern in %s: mux=%s, add=%s\n", log_id(module), log_id(mux), log_id(add)); add->fixup_parameters(); mux->fixup_parameters(); + did_something = true; accept; endcode From 8a6c1005e3afe45a17e2754f40f3341b31528dfe Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 17 Dec 2024 15:45:36 -0800 Subject: [PATCH 2/2] Clean after opt --- tests/peepopt/muxadd.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/peepopt/muxadd.ys b/tests/peepopt/muxadd.ys index 261cdc284..6d36de54c 100644 --- a/tests/peepopt/muxadd.ys +++ b/tests/peepopt/muxadd.ys @@ -13,7 +13,7 @@ module top(a, b, s, y); endmodule EOF check -assert -equiv_opt -assert peepopt +equiv_opt -assert peepopt ;;; design -load postopt select -assert-any t:$add %co1 %a w:y %i # assert adder rewired