All tests pass

This commit is contained in:
Alain Dargelas 2024-12-20 12:05:35 -08:00
parent 095bf92bdc
commit cd503d4c0f
1 changed files with 2 additions and 2 deletions

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@ -91,8 +91,8 @@ code add_y add_a add_b add_a_ext add_a_id add_b_id mux_y mux_a mux_b mux_a_id m
} }
} }
// Create new mid wire // Create new mid wire
mid = module->addWire(NEW_ID, GetSize(add_b)); mid = module->addWire(NEW_ID, GetSize(add_b));
add->setPort(add_b_id, mid); add->setPort(add_b_id, mid);
add->setPort(add_a_id, add_a); add->setPort(add_a_id, add_a);