All tests pass

This commit is contained in:
Alain Dargelas 2024-12-20 12:04:37 -08:00
parent 7ce046053b
commit 095bf92bdc
1 changed files with 1 additions and 1 deletions

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@ -74,7 +74,7 @@ code add_y add_a add_b add_a_ext add_a_id add_b_id mux_y mux_a mux_b mux_a_id m
}
}
// ...or the port name could be a wire name
if (add_y.is_wire()) {
if (add_y.is_wire()) {
if (adder_y_name.size()) {
if (adder_y_name[0] != '$') {
module->rename(adder_y_name, module->uniquify("$" + adder_y_name));