mirror of https://github.com/YosysHQ/yosys.git
Use choices for addAB, now called postAdd
This commit is contained in:
Eddie Hung
parent
2d80866daf
commit
cd002ad3fb
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@ -39,7 +39,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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log("ffM: %s\n", log_id(st.ffM, "--"));
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log("addAB: %s\n", log_id(st.addAB, "--"));
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log("postAdd: %s\n", log_id(st.postAdd, "--"));
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log("muxAB: %s\n", log_id(st.muxAB, "--"));
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log("ffP: %s\n", log_id(st.ffP, "--"));
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//log("muxP: %s\n", log_id(st.muxP, "--"));
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@ -53,10 +53,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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SigSpec C = st.sigC;
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SigSpec P = st.sigP;
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if (st.addAB) {
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log_assert(st.addAB->getParam("\\A_SIGNED").as_bool());
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log_assert(st.addAB->getParam("\\B_SIGNED").as_bool());
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log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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if (st.postAdd) {
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log_assert(st.postAdd->getParam("\\A_SIGNED").as_bool());
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log_assert(st.postAdd->getParam("\\B_SIGNED").as_bool());
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log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
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SigSpec &opmode = cell->connections_.at("\\OPMODE");
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if (st.ffP && st.muxAB) {
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@ -72,7 +72,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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opmode[6] = State::S0;
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opmode[5] = State::S1;
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pm.autoremove(st.addAB);
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pm.autoremove(st.postAdd);
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}
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if (st.clock != SigBit())
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@ -3,7 +3,8 @@ pattern xilinx_dsp
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state <SigBit> clock
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state <std::set<SigBit>> sigAset sigBset
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state <SigSpec> sigC sigM sigMused sigP sigPused
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state <Cell*> addAB muxAB
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state <Cell*> postAdd muxAB
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state <IdString> postAddAB
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match dsp
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select dsp->type.in(\DSP48E1)
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@ -100,43 +101,25 @@ code clock sigM sigP
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sigP = sigM;
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endcode
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match addA
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select addA->type.in($add)
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select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool()
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select nusers(port(addA, \A)) == 2
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//index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int()) // TODO: Why doesn't this work!?!
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filter GetSize(port(addA, \A)) <= GetSize(sigP)
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filter port(addA, \A) == sigP.extract(0, GetSize(port(addA, \A)))
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filter nusers(sigP.extract_end(GetSize(port(addA, \A)))) <= 1
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match postAdd
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// Ensure that Z mux is not already used
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if port(dsp, \OPMODE).extract(4,3).is_fully_zero()
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select postAdd->type.in($postAdd)
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select param(postAdd, \A_SIGNED).as_bool() && param(postAdd, \B_SIGNED).as_bool()
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choice <IdString> AB {\A, \B}
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define <IdString> AB_WIDTH (AB == \A ? \A_WIDTH : \B_WIDTH)
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select nusers(port(postAdd, AB)) == 2
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filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
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filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
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filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1
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set postAddAB AB
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optional
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endmatch
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match addB
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if !addA
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select addB->type.in($add, $sub)
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select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool()
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index <int> nusers(port(addB, \B)) === 2
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//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int()) // TODO: Why doesn't this work!?!
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filter GetSize(port(addB, \B)) <= GetSize(sigP)
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filter port(addB, \B) == sigP.extract(0, GetSize(port(addB, \B)))
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filter nusers(sigP.extract_end(GetSize(port(addB, \B)))) <= 1
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optional
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endmatch
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code addAB sigC sigP
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if (addA) {
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addAB = addA;
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sigC = port(addAB, \B);
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}
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if (addB) {
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addAB = addB;
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sigC = port(addAB, \A);
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}
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if (addAB) {
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// Ensure that adder is not used
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SigSpec opmodeZ = port(dsp, \OPMODE).extract(4,3);
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if (!opmodeZ.is_fully_zero())
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reject;
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code sigC sigP
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if (postAdd) {
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sigC = port(postAdd, postAddAB == \A ? \B : \A);
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// TODO for DSP48E1, which will have sign extended inputs/outputs
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//int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
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@ -145,10 +128,10 @@ code addAB sigC sigP
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//if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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// reject;
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//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
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//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(postAdd, \A_SIGNED).as_bool()))
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// reject;
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sigP = port(addAB, \Y);
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sigP = port(postAdd, \Y);
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}
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endcode
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@ -190,7 +173,7 @@ code ffP sigP clock
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endcode
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match muxA
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if addAB
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if postAdd
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select muxA->type.in($mux)
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select nusers(port(muxA, \Y)) == 2
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index <SigSpec> port(muxA, \A) === sigP
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@ -199,7 +182,7 @@ match muxA
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endmatch
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match muxB
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if addAB
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if postAdd
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select muxB->type.in($mux)
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select nusers(port(muxB, \Y)) == 2
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index <SigSpec> port(muxB, \B) === sigP
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@ -217,7 +200,7 @@ code sigC muxAB
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sigC = port(muxAB, \A);
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}
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if (muxAB) {
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// Ensure that adder is not used
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// Ensure that postAdder is not used
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SigSpec opmodeZ = port(dsp, \OPMODE).extract(4,3);
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if (!opmodeZ.is_fully_zero())
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reject;
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