yosys/passes/pmgen/xilinx_dsp.pmg

pattern xilinx_dsp

state <SigBit> clock
state <std::set<SigBit>> sigAset sigBset
state <SigSpec> sigC sigM sigMused sigP sigPused
state <Cell*> postAdd muxAB
state <IdString> postAddAB

match dsp
	select dsp->type.in(\DSP48E1)
endmatch

code sigAset sigBset
	SigSpec A = port(dsp, \A);
	A.remove_const();
	sigAset = A.to_sigbit_set();
	SigSpec B = port(dsp, \B);
	B.remove_const();
	sigBset = B.to_sigbit_set();
endcode

code sigM
	sigM = port(dsp, \P);
	//if (GetSize(sigH) <= 10)
	//	reject;
endcode

match ffA
	if param(dsp, \AREG).as_int() == 0
	if !sigAset.empty()
	select ffA->type.in($dff)
	// DSP48E1 does not support clock inversion
	select param(ffA, \CLK_POLARITY).as_bool()
	filter includes(port(ffA, \Q).to_sigbit_set(), sigAset)
	optional
endmatch

code clock
	if (ffA) {
		clock = port(ffA, \CLK).as_bit();

		for (auto b : port(ffA, \Q))
			if (b.wire->get_bool_attribute(\keep))
				reject;
	}
endcode

match ffB
	if param(dsp, \BREG).as_int() == 0
	if !sigBset.empty()
	select ffB->type.in($dff)
	// DSP48E1 does not support clock inversion
	select param(ffB, \CLK_POLARITY).as_bool()
	filter includes(port(ffB, \Q).to_sigbit_set(), sigBset)
	optional
endmatch

code clock
	if (ffB) {
		for (auto b : port(ffB, \Q))
			if (b.wire->get_bool_attribute(\keep))
				reject;

		SigBit c = port(ffB, \CLK).as_bit();

		if (clock != SigBit() && c != clock)
			reject;

		clock = c;
	}
endcode

match ffM
	if param(dsp, \MREG).as_int() == 0
	select ffM->type.in($dff)
	// DSP48E1 does not support clock inversion
	select param(ffM, \CLK_POLARITY).as_bool()
	select nusers(port(ffM, \D)) == 2
	//index <SigSpec> port(ffM, \D) === sigM.extract(0, GetSize(port(ffM, \D))) // TODO: Why doesn't this work!?!
	filter GetSize(port(ffM, \D)) <= GetSize(sigM)
	filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
	filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1
	optional
endmatch

code clock sigM sigP
	if (ffM) {
		sigM = port(ffM, \Q);
		for (auto b : sigM)
			if (b.wire->get_bool_attribute(\keep))
				reject;

		SigBit c = port(ffM, \CLK).as_bit();

		if (clock != SigBit() && c != clock)
			reject;

		clock = c;
	}

	sigP = sigM;
endcode

match postAdd
	// Ensure that Z mux is not already used
	if port(dsp, \OPMODE).extract(4,3).is_fully_zero()

	select postAdd->type.in($postAdd)
	select param(postAdd, \A_SIGNED).as_bool() && param(postAdd, \B_SIGNED).as_bool()
	choice <IdString> AB {\A, \B}
	define <IdString> AB_WIDTH (AB == \A ? \A_WIDTH : \B_WIDTH)
	select nusers(port(postAdd, AB)) == 2
	filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
	filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
	filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1
	set postAddAB AB
	optional
endmatch

code sigC sigP
	if (postAdd) {
		sigC = port(postAdd, postAddAB == \A ? \B : \A);

		// TODO for DSP48E1, which will have sign extended inputs/outputs
		//int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
		//int actual_mul_width = GetSize(sigP);
		//int actual_acc_width = GetSize(sigC);

		//if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
		//	reject;
		//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(postAdd, \A_SIGNED).as_bool()))
		//	reject;

		sigP = port(postAdd, \Y);
	}
endcode

// Extract the bits of P that actually have a consumer
// (as opposed to being a dummy)
code sigPused
	for (int i = 0; i < GetSize(sigP); i++)
		if (sigP[i].wire && nusers(sigP[i]) > 1)
			sigPused.append(sigP[i]);
endcode

match ffP
	if param(dsp, \PREG).as_int() == 0
	if !sigPused.empty()
	if nusers(sigPused) == 2
	select ffP->type.in($dff)
	// DSP48E1 does not support clock inversion
	select param(ffP, \CLK_POLARITY).as_bool()
	filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
	filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
	optional
endmatch

code ffP sigP clock
	if (ffP) {
		for (auto b : port(ffP, \Q))
			if (b.wire->get_bool_attribute(\keep))
				reject;

		SigBit c = port(ffP, \CLK).as_bit();

		if (clock != SigBit() && c != clock)
			reject;

		clock = c;

		sigP = port(ffP, \Q);
	}
endcode

match muxA
	if postAdd
	select muxA->type.in($mux)
	select nusers(port(muxA, \Y)) == 2
	index <SigSpec> port(muxA, \A) === sigP
	index <SigSpec> port(muxA, \Y) === sigC
	optional
endmatch

match muxB
	if postAdd
	select muxB->type.in($mux)
	select nusers(port(muxB, \Y)) == 2
	index <SigSpec> port(muxB, \B) === sigP
	index <SigSpec> port(muxB, \Y) === sigC
	optional
endmatch

code sigC muxAB
	if (muxA) {
		muxAB = muxA;
		sigC = port(muxAB, \B);
	}
	if (muxB) {
		muxAB = muxB;
		sigC = port(muxAB, \A);
	}
	if (muxAB) {
		// Ensure that postAdder is not used
		SigSpec opmodeZ = port(dsp, \OPMODE).extract(4,3);
		if (!opmodeZ.is_fully_zero())
			reject;
	}
endcode

code
	accept;
endcode