riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

opt_expr to trim A port of $shiftx if Y_WIDTH == 1

This commit is contained in:
Eddie Hung 2019-08-21 19:18:05 -07:00
parent 7e7965ca7b
commit c7859531c2
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
passes/opt/opt_expr.cc
View File

@ -745,6 +745,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
} }
if (cell->type == ID($shiftx) && cell->getPort(ID::Y).size() == 1) {
SigSpec sig_a = assign_map(cell->getPort(ID::A));
int width;
for (width = GetSize(sig_a); width > 1; width--) {
if (sig_a[width-1] != State::Sx)
break;
}
if (width < GetSize(sig_a)) {
sig_a.remove(width, GetSize(sig_a)-width);
cell->setPort(ID::A, sig_a);
cell->setParam(ID(A_WIDTH), width);
did_something = true;
goto next_cell;
}
}
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID::Y).size() == 1 && if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID::Y).size() == 1 &&
invert_map.count(assign_map(cell->getPort(ID::A))) != 0) { invert_map.count(assign_map(cell->getPort(ID::A))) != 0) {
cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());