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verilog: fix leaking of type names in parser

This commit is contained in:
Xiretza 2021-03-18 21:52:06 +01:00 committed by Zachary Snow
parent b57e47fad8
commit c6681508f1
1 changed files with 2 additions and 0 deletions
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2
frontends/verilog/verilog_parser.y
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@ -692,6 +692,7 @@ wire_type_token:
astbuf3->is_custom_type = true; astbuf3->is_custom_type = true;
astbuf3->children.push_back(new AstNode(AST_WIRETYPE)); astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
astbuf3->children.back()->str = *$1; astbuf3->children.back()->str = *$1;
delete $1;
} | } |
TOK_WOR { TOK_WOR {
astbuf3->is_wor = true; astbuf3->is_wor = true;
@ -1458,6 +1459,7 @@ param_type:
astbuf1->is_custom_type = true; astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE)); astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
astbuf1->children.back()->str = *$1; astbuf1->children.back()->str = *$1;
delete $1;
}; };
param_decl: param_decl: