riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added support for constant signals in "extract" pass

This commit is contained in:
Clifford Wolf 2013-02-27 13:35:30 +01:00
parent b02e140030
commit c59d77aa30
1 changed files with 18 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
passes/extract/extract.cc
View File

@ -71,6 +71,11 @@ namespace
auto &chunk = conn_sig.chunks[i]; auto &chunk = conn_sig.chunks[i];
assert(chunk.width == 1); assert(chunk.width == 1);
if (chunk.wire == NULL) {
graph.createConstant(cell->name, conn.first, i, int(chunk.data.bits[0]));
continue;
}
if (sig_bit_ref.count(chunk) == 0) { if (sig_bit_ref.count(chunk) == 0) {
bit_ref_t &bit_ref = sig_bit_ref[chunk]; bit_ref_t &bit_ref = sig_bit_ref[chunk];
bit_ref.cell = cell->name; bit_ref.cell = cell->name;
@ -187,6 +192,11 @@ struct ExtractPass : public Pass {
log("Solving for %s in %s.\n", needle_it.first.c_str(), haystack_it.first.c_str()); log("Solving for %s in %s.\n", needle_it.first.c_str(), haystack_it.first.c_str());
solver.solve(results, needle_it.first, haystack_it.first, false); solver.solve(results, needle_it.first, haystack_it.first, false);
} }
log("Found %zd matches.\n", results.size());
if (results.size() > 0)
{
log_header("Substitute SubCircuits with cells.\n");
for (int i = 0; i < int(results.size()); i++) { for (int i = 0; i < int(results.size()); i++) {
log("\nMatch #%d: (%s in %s)\n", i, results[i].needleGraphId.c_str(), results[i].haystackGraphId.c_str()); log("\nMatch #%d: (%s in %s)\n", i, results[i].needleGraphId.c_str(), results[i].haystackGraphId.c_str());
@ -197,6 +207,7 @@ struct ExtractPass : public Pass {
log("\n"); log("\n");
} }
} }
}
delete map; delete map;
log_pop(); log_pop();