mirror of https://github.com/YosysHQ/yosys.git
Added GreenPAK4 skeleton
This commit is contained in:
Clifford Wolf
parent
e7c018e5d1
commit
c5352f45c3
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OBJS += techlibs/greenpak4/synth_greenpak4.o
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
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module \$_DFF_P_ (input D, C, output Q);
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DFF _TECHMAP_REPLACE_ (
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.D(D),
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.Q(Q),
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.CLK(C),
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.nRSTZ(1'b1),
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.nSETZ(1'b1)
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);
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endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(1'b0));
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end else
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if (WIDTH == 2) begin
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LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]));
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end else
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if (WIDTH == 3) begin
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LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
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end else
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if (WIDTH == 4) begin
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LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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module DFF(input D, CLK, nRSTZ, nSETZ, output reg Q);
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always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin
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if (!nRSTZ)
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Q <= 1'b0;
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else if (!nSETZ)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule
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module LUT2(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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endmodule
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module LUT3(input IN0, IN1, IN2, output OUT);
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parameter [7:0] INIT = 0;
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assign OUT = INIT[{IN2, IN1, IN0}];
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endmodule
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module LUT4(input IN0, IN1, IN2, IN3, output OUT);
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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@ -0,0 +1,229 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
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{
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if (label == run_from)
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active = true;
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if (label == run_to)
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active = false;
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return active;
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}
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struct SynthIce40Pass : public Pass {
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SynthIce40Pass() : Pass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_greenpak4 [options]\n");
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log("\n");
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log("This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -blif <file>\n");
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log(" write the design to the specified BLIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified edif file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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log("\n");
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log(" begin:\n");
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log(" read_verilog -lib +/greenpak4/cells_sim.v\n");
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log(" hierarchy -check -top <top>\n");
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log("\n");
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log(" flatten: (unless -noflatten)\n");
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log(" proc\n");
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log(" flatten\n");
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log(" tribuf -logic\n");
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log("\n");
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log(" coarse:\n");
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log(" synth -run coarse\n");
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log("\n");
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log(" fine:\n");
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log(" opt -fast -mux_undef -undriven -fine\n");
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log(" memory_map\n");
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log(" opt -undriven -fine\n");
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log(" techmap\n");
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log(" abc -dff (only if -retime)\n");
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log("\n");
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log(" map_luts:\n");
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log(" abc -lut 4\n");
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log(" clean\n");
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log("\n");
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log(" map_cells:\n");
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log(" techmap -map +/greenpak4/cells_map.v\n");
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log(" clean\n");
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log("\n");
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log(" check:\n");
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log(" hierarchy -check\n");
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log(" stat\n");
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log(" check -noinit\n");
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log("\n");
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log(" blif:\n");
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log(" write_blif -gates -attr -param <file-name>\n");
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log("\n");
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log(" edif:\n");
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log(" write_edif <file-name>\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string top_opt = "-auto-top";
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std::string run_from, run_to;
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std::string blif_file, edif_file;
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bool flatten = true;
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bool retime = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-blif" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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bool active = run_from.empty();
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log_header("Executing SYNTH_GREENPAK4 pass.\n");
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log_push();
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if (check_label(active, run_from, run_to, "begin"))
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{
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Pass::call(design, "read_verilog -lib +/greenpak4/cells_sim.v");
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Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
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}
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if (flatten && check_label(active, run_from, run_to, "flatten"))
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{
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Pass::call(design, "proc");
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Pass::call(design, "flatten");
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Pass::call(design, "tribuf -logic");
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}
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if (check_label(active, run_from, run_to, "coarse"))
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{
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Pass::call(design, "synth -run coarse");
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}
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if (check_label(active, run_from, run_to, "fine"))
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{
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Pass::call(design, "opt -fast -mux_undef -undriven -fine");
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Pass::call(design, "memory_map");
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Pass::call(design, "opt -undriven -fine");
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Pass::call(design, "techmap");
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if (retime)
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Pass::call(design, "abc -dff");
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}
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "abc -lut 4");
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Pass::call(design, "clean");
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}
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if (check_label(active, run_from, run_to, "map_cells"))
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{
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Pass::call(design, "techmap -map +/greenpak4/cells_map.v");
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Pass::call(design, "clean");
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}
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if (check_label(active, run_from, run_to, "check"))
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{
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Pass::call(design, "hierarchy -check");
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Pass::call(design, "stat");
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Pass::call(design, "check -noinit");
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}
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if (check_label(active, run_from, run_to, "blif"))
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{
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if (!blif_file.empty())
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Pass::call(design, stringf("write_blif -gates -attr -param %s", blif_file.c_str()));
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}
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if (check_label(active, run_from, run_to, "edif"))
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{
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if (!edif_file.empty())
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Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
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}
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log_pop();
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}
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} SynthIce40Pass;
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PRIVATE_NAMESPACE_END
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