riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

docs: document simulation time format specifiers

This commit is contained in:
Charlotte 2023-06-28 11:51:22 +10:00 committed by Marcelina Kościelnicka
parent 75b44f21d1
commit c391ee7a0d
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
docs/source/CHAPTER_CellLib.rst
View File

@ -698,6 +698,7 @@ base
* ``d`` for base-10 integers (decimal) * ``d`` for base-10 integers (decimal)
* ``h`` for base-16 integers (hexadecimal) * ``h`` for base-16 integers (hexadecimal)
* ``c`` for ASCII characters/strings * ``c`` for ASCII characters/strings
* ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and :verilog:`$realtime`)
For integers, these items follow: For integers, these items follow:
@ -716,6 +717,8 @@ signedness
ASCII characters/strings have no special options, but the signal size must be ASCII characters/strings have no special options, but the signal size must be
divisible by 8. divisible by 8.
For simulation time, the signal size must be zero.
Finally: Finally:
``}`` ``}``
@ -730,6 +733,8 @@ Some example format specifiers:
+ ``{16:< 10h0u}`` - 16-bit unsigned integer rendered as hexadecimal, + ``{16:< 10h0u}`` - 16-bit unsigned integer rendered as hexadecimal,
zero-padded to fit the largest signal value (4 characters for hex), zero-padded to fit the largest signal value (4 characters for hex),
left-justified, space-padded to 10 characters wide. left-justified, space-padded to 10 characters wide.
+ ``{0:>010t}`` - simulation time, right-justified, zero-padded to 10 characters
wide.
To include literal ``{`` and ``}`` characters in your format string, use ``{{`` To include literal ``{`` and ``}`` characters in your format string, use ``{{``
and ``}}`` respectively. and ``}}`` respectively.