From c391ee7a0d5be7d1fba0da1cd02da14138afdb35 Mon Sep 17 00:00:00 2001 From: Charlotte Date: Wed, 28 Jun 2023 11:51:22 +1000 Subject: [PATCH] docs: document simulation time format specifiers --- docs/source/CHAPTER_CellLib.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/docs/source/CHAPTER_CellLib.rst b/docs/source/CHAPTER_CellLib.rst index 0fae4f44b..a4f986f75 100644 --- a/docs/source/CHAPTER_CellLib.rst +++ b/docs/source/CHAPTER_CellLib.rst @@ -698,6 +698,7 @@ base * ``d`` for base-10 integers (decimal) * ``h`` for base-16 integers (hexadecimal) * ``c`` for ASCII characters/strings + * ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and :verilog:`$realtime`) For integers, these items follow: @@ -716,6 +717,8 @@ signedness ASCII characters/strings have no special options, but the signal size must be divisible by 8. +For simulation time, the signal size must be zero. + Finally: ``}`` @@ -730,6 +733,8 @@ Some example format specifiers: + ``{16:< 10h0u}`` - 16-bit unsigned integer rendered as hexadecimal, zero-padded to fit the largest signal value (4 characters for hex), left-justified, space-padded to 10 characters wide. ++ ``{0:>010t}`` - simulation time, right-justified, zero-padded to 10 characters + wide. To include literal ``{`` and ``}`` characters in your format string, use ``{{`` and ``}}`` respectively.