riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

xilinx_dsp to be sensitive to keep attribute

This commit is contained in:
Eddie Hung 2019-08-15 12:34:11 -07:00
parent 96ee7b9cf7
commit c320abc3f4
1 changed files with 14 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
passes/pmgen/xilinx_dsp.pmg
View File

@ -29,8 +29,13 @@ match ffA
endmatch endmatch
code clock code clock
if (ffA) if (ffA) {
clock = port(ffA, \CLK).as_bit(); clock = port(ffA, \CLK).as_bit();
for (auto b : port(ffA, \Q))
if (b.wire->get_bool_attribute(\keep))
reject;
}
endcode endcode
match ffB match ffB
@ -45,6 +50,10 @@ endmatch
code clock code clock
if (ffB) { if (ffB) {
for (auto b : port(ffB, \Q))
if (b.wire->get_bool_attribute(\keep))
reject;
SigBit c = port(ffB, \CLK).as_bit(); SigBit c = port(ffB, \CLK).as_bit();
if (clock != SigBit() && c != clock) if (clock != SigBit() && c != clock)
@ -156,6 +165,10 @@ code ffP clock
// ffP = ffY; // ffP = ffY;
if (ffP) { if (ffP) {
for (auto b : port(ffP, \Q))
if (b.wire->get_bool_attribute(\keep))
reject;
SigBit c = port(ffP, \CLK).as_bit(); SigBit c = port(ffP, \CLK).as_bit();
if (clock != SigBit() && c != clock) if (clock != SigBit() && c != clock)