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clockgate: 1-bit const 0
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@ -187,7 +187,7 @@ struct ClockgatePass : public Pass {
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icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
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// Tie low DFT ports like scan chain enable
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for (auto port : tie_lo_ports)
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icg->setPort(port, Const(0));
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icg->setPort(port, Const(0, 1));
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// Fix CE polarity if needed
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if (!clk.pol_ce) {
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SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit);
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