From be7c93ec6d3503b5c6feda9f069d02c6eb272de8 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 16 Sep 2024 13:58:27 +0200
Subject: [PATCH] clockgate: 1-bit const 0

---
 passes/techmap/clockgate.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc
index 89eb342fe..da40ae076 100644
--- a/passes/techmap/clockgate.cc
+++ b/passes/techmap/clockgate.cc
@@ -187,7 +187,7 @@ struct ClockgatePass : public Pass {
 				icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
 				// Tie low DFT ports like scan chain enable
 				for (auto port : tie_lo_ports)
-					icg->setPort(port, Const(0));
+					icg->setPort(port, Const(0, 1));
 				// Fix CE polarity if needed
 				if (!clk.pol_ce) {
 					SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit);