WIP

backends/aiger/xaiger.cc

@@ -619,90 +619,30 @@ struct XAigerWriter
 		//	write_o_buffer(0);
 
 		if (!box_list.empty() || !ff_bits.empty()) {
-			RTLIL::Module *holes_module = module->design->addModule("$__holes__");
+			RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
 			log_assert(holes_module);
 
 			dict<IdString, Cell*> cell_cache;
 
-			int port_id = 1;
 			int box_count = 0;
 			for (auto cell : box_list) {
-				RTLIL::Module* orig_box_module = module->design->module(cell->type);
+				RTLIL::Module* box_module = module->design->module(cell->type);
-				log_assert(orig_box_module);
+				log_assert(box_module);
-				IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
-				RTLIL::Module* box_module = module->design->module(derived_name);
-				if (box_module->has_processes())
-					Pass::call_on_module(module->design, box_module, "proc");
-
-				auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
-				Cell *holes_cell = r.first->second;
-				if (r.second && box_module->get_bool_attribute("\\whitebox")) {
-					holes_cell = holes_module->addCell(cell->name, cell->type);
-					holes_cell->parameters = cell->parameters;
-					r.first->second = holes_cell;
-				}
 
 				int box_inputs = 0, box_outputs = 0;
-				for (auto port_name : box_ports.at(cell->type)) {
+				for (auto port_name : box_module->ports) {
 					RTLIL::Wire *w = box_module->wire(port_name);
 					log_assert(w);
-					RTLIL::Wire *holes_wire;
-					RTLIL::SigSpec port_sig;
-
 					if (w->port_input)
-						for (int i = 0; i < GetSize(w); i++) {
+						box_inputs += GetSize(w);
-							box_inputs++;
+					if (w->port_output)
-							holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
-							if (!holes_wire) {
-								holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
-								holes_wire->port_input = true;
-								holes_wire->port_id = port_id++;
-								holes_module->ports.push_back(holes_wire->name);
-							}
-							if (holes_cell)
-								port_sig.append(holes_wire);
-						}
-					if (w->port_output) {
 						box_outputs += GetSize(w);
-						for (int i = 0; i < GetSize(w); i++) {
-							if (GetSize(w) == 1)
-								holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
-							else
-								holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
-							holes_wire->port_output = true;
-							holes_wire->port_id = port_id++;
-							holes_module->ports.push_back(holes_wire->name);
-							if (holes_cell)
-								port_sig.append(holes_wire);
-							else
-								holes_module->connect(holes_wire, State::S0);
-						}
-					}
-					if (!port_sig.empty()) {
-						if (r.second)
-							holes_cell->setPort(w->name, port_sig);
-						else
-							holes_module->connect(holes_cell->getPort(w->name), port_sig);
-					}
 				}
 
 				// For flops only, create an extra 1-bit input that drives a new wire
 				//   called "<cell>.abc9_ff.Q" that is used below
-				if (box_module->get_bool_attribute("\\abc9_flop")) {
+				if (box_module->get_bool_attribute("\\abc9_flop"))
-					log_assert(holes_cell);
-
 					box_inputs++;
-					Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
-					if (!holes_wire) {
-						holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
-						holes_wire->port_input = true;
-						holes_wire->port_id = port_id++;
-						holes_module->ports.push_back(holes_wire->name);
-					}
-					Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
-					log_assert(w);
-					holes_module->connect(w, holes_wire);
-				}
 
 				write_h_buffer(box_inputs);
 				write_h_buffer(box_outputs);
@@ -764,6 +704,7 @@ struct XAigerWriter
 				// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
 				//   since boxes may contain parameters in which case `flatten` would have
 				//   created a new $paramod ...
+				Pass::call_on_module(holes_module->design, holes_module, "wbflip");
 				Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
 
 				dict<SigSig, SigSig> replace;

passes/techmap/abc9.cc

@@ -195,7 +195,11 @@ struct Abc9Pass : public ScriptPass
 		if (dff_mode)
 			run("abc9_ops -prep_dff");
 //		run("opt -purge @abc9_holes");
-//		run("wbflip @abc9_holes");
+
+		run("abc9_ops -prep_holes");
+
+		run("select -set abc9_holes A:abc9_holes");
+		run("wbflip @abc9_holes");
 
 		auto selected_modules = active_design->selected_modules();
 		active_design->selection_stack.emplace_back(false);

passes/techmap/abc9_ops.cc

@@ -288,8 +288,6 @@ void prep_holes(RTLIL::Module *module)
 
 		// Fully pad all unused input connections of this box cell with S0
 		// Fully pad all undriven output connections of this box cell with anonymous wires
-		// NB: Assume box_module->ports are sorted alphabetically
-		//     (as RTLIL::Module::fixup_ports() would do)
 		for (const auto &port_name : box_module->ports) {
 			RTLIL::Wire* w = box_module->wire(port_name);
 			log_assert(w);
@@ -333,6 +331,7 @@ void prep_holes(RTLIL::Module *module)
 	holes_module->set_bool_attribute("\\abc9_holes");
 
 	dict<IdString, Cell*> cell_cache;
+	dict<IdString, std::vector<IdString>> box_ports;
 
 	int port_id = 1;
 	for (auto cell : box_list) {
@@ -350,24 +349,47 @@ void prep_holes(RTLIL::Module *module)
 			holes_cell = holes_module->addCell(cell->name, cell->type);
 			holes_cell->parameters = cell->parameters;
 			r.first->second = holes_cell;
+		}
 
-			// Since Module::derive() will create a new module, there
+		auto r2 = box_ports.insert(cell->type);
-			//   is a chance that the ports will be alphabetically ordered
+		if (r2.second) {
-			//   again, which is a problem when carry-chains are involved.
+			// Make carry in the last PI, and carry out the last PO
-			//   Inherit the port ordering from the original module here...
+			//   since ABC requires it this way
-			//   (and set the port_id below, when iterating through those)
+			IdString carry_in, carry_out;
-			log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
+			for (const auto &port_name : box_module->ports) {
-			box_module->ports = orig_box_module->ports;
+				auto w = box_module->wire(port_name);
+				log_assert(w);
+				if (w->get_bool_attribute("\\abc9_carry")) {
+					if (w->port_input) {
+						if (carry_in != IdString())
+							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
+						carry_in = port_name;
+					}
+					if (w->port_output) {
+						if (carry_out != IdString())
+							log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
+						carry_out = port_name;
+					}
+				}
+				else
+					r2.first->second.push_back(port_name);
+			}
+
+			if (carry_in != IdString() && carry_out == IdString())
+				log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
+			if (carry_in == IdString() && carry_out != IdString())
+				log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
+			if (carry_in != IdString()) {
+				r2.first->second.push_back(carry_in);
+				r2.first->second.push_back(carry_out);
+			}
 		}
 
 		// NB: Assume box_module->ports are sorted alphabetically
 		//     (as RTLIL::Module::fixup_ports() would do)
-		int box_port_id = 1;
+		for (const auto &port_name : box_ports.at(cell->type)) {
-		for (const auto &port_name : box_module->ports) {
 			RTLIL::Wire *w = box_module->wire(port_name);
 			log_assert(w);
-			if (r.second)
-				w->port_id = box_port_id++;
 			RTLIL::Wire *holes_wire;
 			RTLIL::SigSpec port_sig;
 			if (w->port_input)