mirror of https://github.com/YosysHQ/yosys.git
Added $logic_not handling to fsm_detect
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@ -89,6 +89,8 @@ static bool check_state_users(RTLIL::SigSpec sig)
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RTLIL::Cell *cell = cellport.first;
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RTLIL::Cell *cell = cellport.first;
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if (muxtree_cells.count(cell) > 0)
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if (muxtree_cells.count(cell) > 0)
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continue;
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continue;
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if (cell->type == "$logic_not" && assign_map(cell->getPort("\\A")) == sig)
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continue;
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if (cellport.second != "\\A" && cellport.second != "\\B")
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if (cellport.second != "\\A" && cellport.second != "\\B")
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return false;
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return false;
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if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
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if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
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