Add tests for some common techmap files.

tests/techmap/adff2dff.ys

@@ -0,0 +1,19 @@
+read_verilog -icells << EOT
+module top(...);
+
+input [1:0] D;
+input C, R;
+output [1:0] Q;
+
+always @(posedge C, posedge R)
+  if (R)
+    Q <= 0;
+  else
+    Q <= D;
+
+endmodule
+EOT
+
+proc
+
+equiv_opt -async2sync techmap -map +/adff2dff.v

tests/techmap/dff2ff.ys

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+read_verilog -icells << EOT
+module top(...);
+
+input [1:0] D;
+input C;
+output [1:0] Q;
+
+always @(posedge C)
+  Q <= D;
+
+endmodule
+EOT
+
+proc
+
+equiv_opt techmap -map +/dff2ff.v

tests/techmap/pmux2mux.ys

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+read_verilog -icells << EOT
+module top(...);
+
+input [3:0] A;
+input [3:0] B0;
+input [3:0] B1;
+input [1:0] S;
+output [3:0] O;
+
+\$pmux #(.WIDTH(4), .S_WIDTH(2)) pm (.A(A), .B({B1, B0}), .S(S), .Y(O));
+
+endmodule
+EOT
+
+equiv_opt techmap -map +/pmux2mux.v