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Gowin. Add the EMCU primitive.
EMCU is a micro-processor based on ARM Cortex-M3 embedded in the GW1NSR-4C chip used in the Tangnano4k board. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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@ -1966,5 +1966,103 @@ output CLKOUT;
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parameter DCS_MODE = "RISING";
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endmodule
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(* blackbox *)
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module EMCU (
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input FCLK,
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input PORESETN,
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input SYSRESETN,
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input RTCSRCCLK,
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output [15:0] IOEXPOUTPUTO,
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output [15:0] IOEXPOUTPUTENO,
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input [15:0] IOEXPINPUTI,
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output UART0TXDO,
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output UART1TXDO,
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output UART0BAUDTICK,
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output UART1BAUDTICK,
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input UART0RXDI,
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input UART1RXDI,
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output INTMONITOR,
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output MTXHRESETN,
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output [12:0] SRAM0ADDR,
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output [3:0] SRAM0WREN,
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output [31:0] SRAM0WDATA,
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output SRAM0CS,
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input [31:0] SRAM0RDATA,
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output TARGFLASH0HSEL,
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output [28:0] TARGFLASH0HADDR,
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output [1:0] TARGFLASH0HTRANS,
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output [2:0] TARGFLASH0HSIZE,
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output [2:0] TARGFLASH0HBURST,
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output TARGFLASH0HREADYMUX,
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input [31:0] TARGFLASH0HRDATA,
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input [2:0] TARGFLASH0HRUSER,
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input TARGFLASH0HRESP,
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input TARGFLASH0EXRESP,
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input TARGFLASH0HREADYOUT,
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output TARGEXP0HSEL,
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output [31:0] TARGEXP0HADDR,
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output [1:0] TARGEXP0HTRANS,
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output TARGEXP0HWRITE,
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output [2:0] TARGEXP0HSIZE,
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output [2:0] TARGEXP0HBURST,
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output [3:0] TARGEXP0HPROT,
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output [1:0] TARGEXP0MEMATTR,
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output TARGEXP0EXREQ,
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output [3:0] TARGEXP0HMASTER,
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output [31:0] TARGEXP0HWDATA,
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output TARGEXP0HMASTLOCK,
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output TARGEXP0HREADYMUX,
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output TARGEXP0HAUSER,
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output [3:0] TARGEXP0HWUSER,
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input [31:0] TARGEXP0HRDATA,
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input TARGEXP0HREADYOUT,
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input TARGEXP0HRESP,
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input TARGEXP0EXRESP,
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input [2:0] TARGEXP0HRUSER,
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output [31:0] INITEXP0HRDATA,
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output INITEXP0HREADY,
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output INITEXP0HRESP,
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output INITEXP0EXRESP,
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output [2:0] INITEXP0HRUSER,
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input INITEXP0HSEL,
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input [31:0] INITEXP0HADDR,
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input [1:0] INITEXP0HTRANS,
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input INITEXP0HWRITE,
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input [2:0] INITEXP0HSIZE,
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input [2:0] INITEXP0HBURST,
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input [3:0] INITEXP0HPROT,
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input [1:0] INITEXP0MEMATTR,
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input INITEXP0EXREQ,
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input [3:0] INITEXP0HMASTER,
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input [31:0] INITEXP0HWDATA,
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input INITEXP0HMASTLOCK,
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input INITEXP0HAUSER,
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input [3:0] INITEXP0HWUSER,
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output [3:0] APBTARGEXP2PSTRB,
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output [2:0] APBTARGEXP2PPROT,
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output APBTARGEXP2PSEL,
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output APBTARGEXP2PENABLE,
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output [11:0] APBTARGEXP2PADDR,
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output APBTARGEXP2PWRITE,
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output [31:0] APBTARGEXP2PWDATA,
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input [31:0] APBTARGEXP2PRDATA,
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input APBTARGEXP2PREADY,
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input APBTARGEXP2PSLVERR,
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input [3:0] MTXREMAP,
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output DAPTDO,
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output DAPJTAGNSW,
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output DAPNTDOEN,
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input DAPSWDITMS,
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input DAPTDI,
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input DAPNTRST,
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input DAPSWCLKTCK,
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output [3:0] TPIUTRACEDATA,
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output TPIUTRACECLK,
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input [4:0] GPINT,
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input FLASHERR,
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input FLASHINT
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);
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endmodule
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@ -23,7 +23,7 @@ _skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DF
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'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4',
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'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4',
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'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP',
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'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC'
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'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'DCS', 'EMCU'
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}
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def xtract_cells_decl(dir, fout):
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fname = os.path.join(dir, 'prim_sim.v')
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@ -1699,9 +1699,6 @@ input CLKIN, CE;
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output CLKOUT, CLKOUTN;
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endmodule
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module EMCU (...);
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endmodule
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module FLASH64K (...);
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input[4:0]XADR;
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input[5:0]YADR;
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