From ab35dff702310668b6521466718c56cfd159ec3e Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Wed, 11 Sep 2024 10:18:51 +1000
Subject: [PATCH] Gowin. Add the EMCU primitive.

EMCU is a micro-processor based on ARM Cortex-M3 embedded in the
GW1NSR-4C chip used in the Tangnano4k board.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 techlibs/gowin/cells_sim.v   | 98 ++++++++++++++++++++++++++++++++++++
 techlibs/gowin/cells_xtra.py |  2 +-
 techlibs/gowin/cells_xtra.v  |  3 --
 3 files changed, 99 insertions(+), 4 deletions(-)

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 96121a881..76635355d 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -1966,5 +1966,103 @@ output CLKOUT;
 parameter DCS_MODE = "RISING";
 endmodule
 
+(* blackbox *)
+module EMCU (
+  input          FCLK,
+  input          PORESETN,
+  input          SYSRESETN,
+  input          RTCSRCCLK,
+  output  [15:0] IOEXPOUTPUTO,
+  output  [15:0] IOEXPOUTPUTENO,
+  input   [15:0] IOEXPINPUTI,
+  output         UART0TXDO,
+  output         UART1TXDO,
+  output         UART0BAUDTICK,
+  output         UART1BAUDTICK,
+  input          UART0RXDI,
+  input          UART1RXDI,
+  output         INTMONITOR,
+  output         MTXHRESETN,
+  output  [12:0] SRAM0ADDR,
+  output   [3:0] SRAM0WREN,
+  output  [31:0] SRAM0WDATA,
+  output         SRAM0CS,
+  input   [31:0] SRAM0RDATA,
+  output         TARGFLASH0HSEL,
+  output  [28:0] TARGFLASH0HADDR,
+  output   [1:0] TARGFLASH0HTRANS,
+  output   [2:0] TARGFLASH0HSIZE,
+  output   [2:0] TARGFLASH0HBURST,
+  output         TARGFLASH0HREADYMUX,
+  input   [31:0] TARGFLASH0HRDATA,
+  input    [2:0] TARGFLASH0HRUSER,
+  input          TARGFLASH0HRESP,
+  input          TARGFLASH0EXRESP,
+  input          TARGFLASH0HREADYOUT,
+  output         TARGEXP0HSEL,
+  output  [31:0] TARGEXP0HADDR,
+  output   [1:0] TARGEXP0HTRANS,
+  output         TARGEXP0HWRITE,
+  output   [2:0] TARGEXP0HSIZE,
+  output   [2:0] TARGEXP0HBURST,
+  output   [3:0] TARGEXP0HPROT,
+  output   [1:0] TARGEXP0MEMATTR,
+  output         TARGEXP0EXREQ,
+  output   [3:0] TARGEXP0HMASTER,
+  output  [31:0] TARGEXP0HWDATA,
+  output         TARGEXP0HMASTLOCK,
+  output         TARGEXP0HREADYMUX,
+  output         TARGEXP0HAUSER,
+  output   [3:0] TARGEXP0HWUSER,
+  input   [31:0] TARGEXP0HRDATA,
+  input          TARGEXP0HREADYOUT,
+  input          TARGEXP0HRESP,
+  input          TARGEXP0EXRESP,
+  input    [2:0] TARGEXP0HRUSER,
+  output  [31:0] INITEXP0HRDATA,
+  output         INITEXP0HREADY,
+  output         INITEXP0HRESP,
+  output         INITEXP0EXRESP,
+  output   [2:0] INITEXP0HRUSER,
+  input          INITEXP0HSEL,
+  input   [31:0] INITEXP0HADDR,
+  input    [1:0] INITEXP0HTRANS,
+  input          INITEXP0HWRITE,
+  input    [2:0] INITEXP0HSIZE,
+  input    [2:0] INITEXP0HBURST,
+  input    [3:0] INITEXP0HPROT,
+  input    [1:0] INITEXP0MEMATTR,
+  input          INITEXP0EXREQ,
+  input    [3:0] INITEXP0HMASTER,
+  input   [31:0] INITEXP0HWDATA,
+  input          INITEXP0HMASTLOCK,
+  input          INITEXP0HAUSER,
+  input    [3:0] INITEXP0HWUSER,
+  output   [3:0] APBTARGEXP2PSTRB,
+  output   [2:0] APBTARGEXP2PPROT,
+  output         APBTARGEXP2PSEL,
+  output         APBTARGEXP2PENABLE,
+  output  [11:0] APBTARGEXP2PADDR,
+  output         APBTARGEXP2PWRITE,
+  output  [31:0] APBTARGEXP2PWDATA,
+  input   [31:0] APBTARGEXP2PRDATA,
+  input          APBTARGEXP2PREADY,
+  input          APBTARGEXP2PSLVERR,
+  input    [3:0] MTXREMAP,
+  output         DAPTDO,
+  output         DAPJTAGNSW,
+  output         DAPNTDOEN,
+  input          DAPSWDITMS,
+  input          DAPTDI,
+  input          DAPNTRST,
+  input          DAPSWCLKTCK,
+  output   [3:0] TPIUTRACEDATA,
+  output         TPIUTRACECLK,
+  input    [4:0] GPINT,
+  input          FLASHERR,
+  input          FLASHINT
+
+ );
+endmodule
 
 
diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py
index 224ece02f..3f0047ecb 100644
--- a/techlibs/gowin/cells_xtra.py
+++ b/techlibs/gowin/cells_xtra.py
@@ -23,7 +23,7 @@ _skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DF
           'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4',
           'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4',
           'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP',
-          'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC'
+          'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'DCS', 'EMCU'
         }
 def xtract_cells_decl(dir, fout):
     fname = os.path.join(dir, 'prim_sim.v')
diff --git a/techlibs/gowin/cells_xtra.v b/techlibs/gowin/cells_xtra.v
index 6ab50a097..4cb4bab2f 100644
--- a/techlibs/gowin/cells_xtra.v
+++ b/techlibs/gowin/cells_xtra.v
@@ -1699,9 +1699,6 @@ input CLKIN, CE;
 output CLKOUT, CLKOUTN;
 endmodule
 
-module EMCU (...);
-endmodule
-
 module FLASH64K (...);
 input[4:0]XADR;
 input[5:0]YADR;