mirror of https://github.com/YosysHQ/yosys.git
Added avail params to ilang format, check module params in 'hierarchy -check'
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3655d7fea7
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@ -278,6 +278,13 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
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}
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}
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f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
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f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
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if (!module->avail_parameters.empty()) {
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if (only_selected)
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f << stringf("\n");
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for (auto &p : module->avail_parameters)
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f << stringf("%s" " parameter %s\n", indent.c_str(), p.c_str());
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}
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}
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}
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if (print_body)
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if (print_body)
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@ -934,10 +934,15 @@ static AstModule* process_module(AstNode *ast, bool defer)
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if (flag_lib) {
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if (flag_lib) {
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std::vector<AstNode*> new_children;
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std::vector<AstNode*> new_children;
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for (auto child : ast->children) {
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for (auto child : ast->children) {
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if (child->type == AST_WIRE && (child->is_input || child->is_output))
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if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
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new_children.push_back(child);
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new_children.push_back(child);
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else
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} else if (child->type == AST_PARAMETER) {
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child->delete_children();
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child->children.push_back(AstNode::mkconst_int(0, false, 0));
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new_children.push_back(child);
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} else {
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delete child;
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delete child;
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}
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}
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}
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ast->children.swap(new_children);
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ast->children.swap(new_children);
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ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
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ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
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@ -112,7 +112,13 @@ module_body:
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/* empty */;
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/* empty */;
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module_stmt:
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module_stmt:
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attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
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param_stmt | attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
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param_stmt:
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TOK_PARAMETER TOK_ID EOL {
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current_module->avail_parameters.insert($2);
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free($2);
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};
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attr_stmt:
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attr_stmt:
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TOK_ATTRIBUTE TOK_ID constant EOL {
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TOK_ATTRIBUTE TOK_ID constant EOL {
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@ -212,6 +212,10 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
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} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
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log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
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log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
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log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
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log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
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for (auto ¶m : cell->parameters)
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if (mod->avail_parameters.count(param.first) == 0)
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log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n",
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log_id(cell->type), log_id(module), log_id(cell), log_id(param.first));
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}
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}
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if (cell->parameters.size() == 0)
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if (cell->parameters.size() == 0)
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