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Implemented same div-by-zero behavior as found in other synthesis tools

This commit is contained in:
Clifford Wolf 2013-08-15 21:00:06 +02:00
parent 78658199e6
commit a860efa8ac
2 changed files with 59 additions and 7 deletions
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33
kernel/satgen.h
View File

@ -300,20 +300,43 @@ struct SatGen
chain_buf.erase(chain_buf.begin() + a_u.size(), chain_buf.end()); chain_buf.erase(chain_buf.begin() + a_u.size(), chain_buf.end());
} }
std::vector<int> y_tmp = ignore_div_by_zero ? y : ez->vec_var(y.size());
if (cell->type == "$div") { if (cell->type == "$div") {
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
ez->assume(ez->vec_eq(y, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u))); ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
else else
ez->assume(ez->vec_eq(y, y_u)); ez->assume(ez->vec_eq(y_tmp, y_u));
} else { } else {
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
ez->assume(ez->vec_eq(y, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf))); ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf)));
else else
ez->assume(ez->vec_eq(y, chain_buf)); ez->assume(ez->vec_eq(y_tmp, chain_buf));
} }
if (ignore_div_by_zero) if (ignore_div_by_zero) {
ez->assume(ez->expression(ezSAT::OpOr, b)); ez->assume(ez->expression(ezSAT::OpOr, b));
} else {
std::vector<int> div_zero_result;
if (cell->type == "$div") {
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) {
std::vector<int> all_ones(y.size(), ez->TRUE);
std::vector<int> only_first_one(y.size(), ez->FALSE);
only_first_one.at(0) = ez->TRUE;
div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
} else {
div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").width, ez->TRUE);
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
}
} else {
int copy_a_bits = std::min(cell->connections.at("\\A").width, cell->connections.at("\\B").width);
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
else
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
}
ez->assume(ez->vec_eq(y, ez->vec_ite(ez->expression(ezSAT::OpOr, b), y_tmp, div_zero_result)));
}
return true; return true;
} }

33
techlibs/stdcells.v
View File

@ -1077,6 +1077,9 @@ input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B; input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] Y_buf;
wire [Y_WIDTH-1:0] Y_div_zero;
\$div_mod #( \$div_mod #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
@ -1086,9 +1089,20 @@ output [Y_WIDTH-1:0] Y;
) div_mod ( ) div_mod (
.A(A), .A(A),
.B(B), .B(B),
.Y(Y) .Y(Y_buf)
); );
// explicitly force the division-by-zero behavior found in other synthesis tools
generate begin
if (A_SIGNED && B_SIGNED) begin:make_div_zero
assign Y_div_zero = A[A_WIDTH-1] ? {Y_WIDTH{1'b0}} | 1'b1 : {Y_WIDTH{1'b1}};
end else begin:make_div_zero
assign Y_div_zero = {A_WIDTH{1'b1}};
end
end endgenerate
assign Y = B ? Y_buf : Y_div_zero;
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
@ -1105,6 +1119,9 @@ input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B; input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] Y_buf;
wire [Y_WIDTH-1:0] Y_div_zero;
\$div_mod #( \$div_mod #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
@ -1114,9 +1131,21 @@ output [Y_WIDTH-1:0] Y;
) div_mod ( ) div_mod (
.A(A), .A(A),
.B(B), .B(B),
.R(Y) .R(Y_buf)
); );
// explicitly force the division-by-zero behavior found in other synthesis tools
localparam div_zero_copy_a_bits = A_WIDTH < B_WIDTH ? A_WIDTH : B_WIDTH;
generate begin
if (A_SIGNED && B_SIGNED) begin:make_div_zero
assign Y_div_zero = $signed(A[div_zero_copy_a_bits-1:0]);
end else begin:make_div_zero
assign Y_div_zero = $unsigned(A[div_zero_copy_a_bits-1:0]);
end
end endgenerate
assign Y = B ? Y_buf : Y_div_zero;
endmodule endmodule
/**** /****