abc9: respect (* keep *) on cells

backends/aiger/xaiger.cc

@@ -186,6 +186,8 @@ struct XAigerWriter
 
 		dict<IdString,dict<IdString,int>> arrival_cache;
 		for (auto cell : module->cells()) {
+			RTLIL::Module* inst_module = module->design->module(cell->type);
+			if (!cell->has_keep_attr()) {
 				if (cell->type == "$_NOT_")
 				{
 					SigBit A = sigmap(cell->getPort("\\A").as_bit());
@@ -223,7 +225,6 @@ struct XAigerWriter
 					continue;
 				}
 
-			RTLIL::Module* inst_module = module->design->module(cell->type);
 				if (inst_module) {
 					auto it = cell->attributes.find("\\abc9_box_seq");
 					if (it != cell->attributes.end()) {
@@ -256,6 +257,7 @@ struct XAigerWriter
 								arrival_times[bit] = arrival;
 					}
 				}
+			}
 
 			bool cell_known = inst_module || cell->known();
 			for (const auto &c : cell->connections()) {
@@ -270,6 +272,9 @@ struct XAigerWriter
 					for (auto b : c.second) {
 						Wire *w = b.wire;
 						if (!w) continue;
+						// Do not add as PO if bit is already a PI
+						if (input_bits.count(b))
+							continue;
 						if (!w->port_output || !cell_known) {
 							SigBit I = sigmap(b);
 							if (I != b)
@@ -431,6 +436,9 @@ struct XAigerWriter
 		for (const auto &bit : output_bits) {
 			ordered_outputs[bit] = aig_o++;
 			int aig;
+			// For inout/keep bits only, the output bit
+			//   should be driven by logic, not the PI,
+			//   so temporarily swap that out
 			if (input_bits.count(bit)) {
 				auto it = aig_map.find(bit);
 				int input_aig = it->second;

passes/techmap/abc9_ops.cc

@@ -489,6 +489,8 @@ void reintegrate(RTLIL::Module *module)
 
 	std::vector<Cell*> boxes;
 	for (auto cell : module->cells().to_vector()) {
+		if (cell->has_keep_attr())
+			continue;
 		if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
 			module->remove(cell);
 		else if (cell->attributes.erase("\\abc9_box_seq"))

tests/techmap/abc9.ys

@@ -51,3 +51,18 @@ simplemap
 equiv_opt -assert abc9 -lut 4
 design -load postopt
 select -assert-count 2 t:$lut
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, b, output o);
+wire w;
+(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
+assign o = ~w;
+endmodule
+EOT
+
+simplemap
+equiv_opt -assert abc9 -lut 4
+design -load postopt
+select -assert-count 1 t:$lut
+select -assert-count 1 t:$_AND_