mirror of https://github.com/YosysHQ/yosys.git
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
This reverts commit 234738b103
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f4387e817c
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a4238637ac
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@ -61,6 +61,8 @@ module _80_mul (A, B, Y);
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input [B_WIDTH-1:0] B;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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generate
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generate
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if (0) begin end
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if (0) begin end
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`ifdef DSP_A_MINWIDTH
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`ifdef DSP_A_MINWIDTH
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@ -75,8 +77,10 @@ module _80_mul (A, B, Y);
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else if (Y_WIDTH < `DSP_Y_MINWIDTH)
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else if (Y_WIDTH < `DSP_Y_MINWIDTH)
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wire _TECHMAP_FAIL_ = 1;
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wire _TECHMAP_FAIL_ = 1;
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`endif
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`endif
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else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)
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wire _TECHMAP_FAIL_ = 1;
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`ifdef DSP_SIGNEDONLY
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`ifdef DSP_SIGNEDONLY
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else if (!A_SIGNED)
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else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)
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\$mul #(
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\$mul #(
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.A_SIGNED(1),
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.A_SIGNED(1),
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.B_SIGNED(1),
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.B_SIGNED(1),
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@ -89,7 +93,7 @@ module _80_mul (A, B, Y);
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.Y(Y)
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.Y(Y)
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);
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);
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`endif
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`endif
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else if (A_WIDTH < B_WIDTH)
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else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
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\$mul #(
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\$mul #(
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.A_SIGNED(B_SIGNED),
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.B_SIGNED(A_SIGNED),
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