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cellhelp: Add source line to help 

Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
This commit is contained in:
Krystine Sherwin 2024-04-12 13:57:51 +12:00
parent 784292626e
commit a2b2904ed8
No known key found for this signature in database
2 changed files with 18 additions and 7 deletions
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4
kernel/register.cc
View File

@ -757,6 +757,7 @@ struct SimHelper {
} }
string title; string title;
string ports; string ports;
string source;
string desc; string desc;
string code; string code;
string ver; string ver;
@ -901,7 +902,8 @@ struct HelpPass : public Pass {
// source code // source code
fprintf(f, "Simulation model (Verilog)\n"); fprintf(f, "Simulation model (Verilog)\n");
fprintf(f, "--------------------------\n\n"); fprintf(f, "--------------------------\n\n");
fprintf(f, ".. code:: verilog\n\n"); fprintf(f, ".. code-block:: verilog\n");
fprintf(f, " :caption: %s\n\n", cell.source.c_str());
std::stringstream ss; std::stringstream ss;
ss << cell.code; ss << cell.code;
for (std::string line; std::getline(ss, line, '\n');) { for (std::string line; std::getline(ss, line, '\n');) {

21
techlibs/common/cellhelp.py
View File

@ -3,11 +3,13 @@
from __future__ import annotations from __future__ import annotations
import fileinput import fileinput
import json import json
from pathlib import Path
class SimHelper: class SimHelper:
name: str = "" name: str = ""
title: str = "" title: str = ""
ports: str = "" ports: str = ""
source: str = ""
desc: list[str] desc: list[str]
code: list[str] code: list[str]
ver: str = "1" ver: str = "1"
@ -16,14 +18,19 @@ class SimHelper:
self.desc = [] self.desc = []
def __str__(self) -> str: def __str__(self) -> str:
printed_fields = [
"name", "title", "ports", "source", "desc", "code", "ver",
]
# generate C++ struct
val = "tempCell = {\n" val = "tempCell = {\n"
val += f' {json.dumps(self.name)},\n' for field in printed_fields:
val += f' {json.dumps(self.title)},\n' field_val = getattr(self, field)
val += f' {json.dumps(self.ports)},\n' if isinstance(field_val, list):
val += ' ' + json.dumps("\n".join(self.desc)) + ',\n' field_val = "\n".join(field_val)
val += ' ' + json.dumps("\n".join(self.code)) + ',\n' val += f' {json.dumps(field_val)},\n'
val += f' {json.dumps(self.ver)},\n'
val += "};\n" val += "};\n"
# map name to struct
val += f'cell_help[{json.dumps(self.name)}] = tempCell;' val += f'cell_help[{json.dumps(self.name)}] = tempCell;'
val += "\n" val += "\n"
val += f'cell_code[{json.dumps(self.name + "+")}] = tempCell;' val += f'cell_code[{json.dumps(self.name + "+")}] = tempCell;'
@ -45,6 +52,8 @@ for line in fileinput.input():
clean_line = line[7:].replace("\\", "").replace(";", "") clean_line = line[7:].replace("\\", "").replace(";", "")
simHelper.name, simHelper.ports = clean_line.split(maxsplit=1) simHelper.name, simHelper.ports = clean_line.split(maxsplit=1)
simHelper.code = [] simHelper.code = []
short_filename = Path(fileinput.filename()).name
simHelper.source = f'{short_filename}:{fileinput.filelineno()}'
elif not line.startswith("endmodule"): elif not line.startswith("endmodule"):
line = " " + line line = " " + line
try: try: