mirror of https://github.com/YosysHQ/yosys.git
Set results of out-of-bounds static bit/part select to undef
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55521c085a
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@ -866,6 +866,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::Wire *wire = NULL;
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RTLIL::Wire *wire = NULL;
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RTLIL::SigChunk chunk;
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RTLIL::SigChunk chunk;
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int add_undef_bits_msb = 0;
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int add_undef_bits_lsb = 0;
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if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
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if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
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RTLIL::Wire *wire = current_module->addWire(str);
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RTLIL::Wire *wire = current_module->addWire(str);
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wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
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wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
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@ -919,17 +922,40 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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delete fake_ast;
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delete fake_ast;
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return sig;
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return sig;
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} else {
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} else {
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if (children[0]->range_left > id2ast->range_left || id2ast->range_right > children[0]->range_right)
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int source_width = id2ast->range_left - id2ast->range_right + 1;
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log_error("Range select out of bounds on signal `%s' at %s:%d!\n",
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str.c_str(), filename.c_str(), linenum);
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chunk.width = children[0]->range_left - children[0]->range_right + 1;
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chunk.width = children[0]->range_left - children[0]->range_right + 1;
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chunk.offset = children[0]->range_right - id2ast->range_right;
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chunk.offset = children[0]->range_right - id2ast->range_right;
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if (id2ast->range_swapped)
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if (id2ast->range_swapped)
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chunk.offset = wire->width - (chunk.offset + chunk.width);
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chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
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if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
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if (chunk.width == 1)
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log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
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str.c_str(), filename.c_str(), linenum);
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else
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log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
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str.c_str(), filename.c_str(), linenum, chunk.width);
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chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
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} else {
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if (chunk.width + chunk.offset > source_width) {
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add_undef_bits_msb = (chunk.width + chunk.offset) - source_width;
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chunk.width -= add_undef_bits_msb;
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}
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if (chunk.offset < 0) {
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add_undef_bits_lsb = -chunk.offset;
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chunk.width -= add_undef_bits_lsb;
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chunk.offset += add_undef_bits_lsb;
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}
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if (add_undef_bits_lsb)
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log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
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str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb);
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if (add_undef_bits_msb)
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log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
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str.c_str(), filename.c_str(), linenum, add_undef_bits_msb);
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}
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}
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}
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}
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}
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RTLIL::SigSpec sig(chunk);
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RTLIL::SigSpec sig = { RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_msb), chunk, RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_lsb) };
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if (genRTLIL_subst_from && genRTLIL_subst_to)
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if (genRTLIL_subst_from && genRTLIL_subst_to)
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sig.replace(*genRTLIL_subst_from, *genRTLIL_subst_to);
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sig.replace(*genRTLIL_subst_from, *genRTLIL_subst_to);
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