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Fix check

This commit is contained in:
Eddie Hung 2019-08-09 14:27:08 -07:00
parent 82cbfada1b
commit a002eba14a
1 changed files with 6 additions and 4 deletions
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10
passes/pmgen/ice40_dsp.pmg
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@ -119,15 +119,16 @@ match addB
endmatch endmatch
code addAB sigCD sigO code addAB sigCD sigO
bool CD_SIGNED = false;
if (addA) { if (addA) {
addAB = addA; addAB = addA;
sigCD = port(addAB, \B); sigCD = port(addAB, \B);
sigCD.extend_u0(32, param(addAB, \B_SIGNED).as_bool()); CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
} }
if (addB) { if (addB) {
addAB = addB; addAB = addB;
sigCD = port(addAB, \A); sigCD = port(addAB, \A);
sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool()); CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
} }
if (addAB) { if (addAB) {
if (mul->type == \SB_MAC16) { if (mul->type == \SB_MAC16) {
@ -139,7 +140,7 @@ code addAB sigCD sigO
int natural_mul_width = GetSize(sigA) + GetSize(sigB); int natural_mul_width = GetSize(sigA) + GetSize(sigB);
int actual_mul_width = GetSize(sigH); int actual_mul_width = GetSize(sigH);
int actual_acc_width = GetSize(sigO); int actual_acc_width = GetSize(sigCD);
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject; reject;
@ -147,6 +148,7 @@ code addAB sigCD sigO
reject; reject;
sigO = port(addAB, \Y); sigO = port(addAB, \Y);
sigCD.extend_u0(32, CD_SIGNED);
} }
endcode endcode
@ -255,7 +257,7 @@ code clock clock_pol sigO sigCD
else if (muxB) else if (muxB)
sigCD = port(muxAB, \A); sigCD = port(muxAB, \A);
else log_abort(); else log_abort();
sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool()); sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
} }
} }
endcode endcode