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More accurate CHANGELOG

This commit is contained in:
Eddie Hung 2019-06-13 08:22:22 -07:00
parent c04482b077
commit 9d34cea65a
1 changed files with 3 additions and 1 deletions
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@ -17,7 +17,9 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "rename -src"
- Added "equiv_opt" pass
- Added "read_aiger" frontend
- Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9)
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"