riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update CHANGELOG

This commit is contained in:
Eddie Hung 2019-06-12 16:54:12 -07:00
parent 2c40b66785
commit c04482b077
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
CHANGELOG
View File

@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "rename -src"
- Added "equiv_opt" pass
- Added "read_aiger" frontend
- Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9)
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"