riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Docs: Fix nested list on build_verific page

This commit is contained in:
Krystine Sherwin 2024-08-26 10:55:01 +12:00
parent 7d63fdd88e
commit 98d26bdd2c
No known key found for this signature in database
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/source/yosys_internals/extending_yosys/build_verific.rst
View File

@ -81,8 +81,10 @@ The following features, along with their corresponding Yosys build parameters,
are required for the Yosys-Verific patch: are required for the Yosys-Verific patch:
* RTL elaboration with * RTL elaboration with
* SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
* VHDL support with ``ENABLE_VERIFIC_VHDL``. * VHDL support with ``ENABLE_VERIFIC_VHDL``.
* Hierarchy tree support and static elaboration with * Hierarchy tree support and static elaboration with
``ENABLE_VERIFIC_HIER_TREE``. ``ENABLE_VERIFIC_HIER_TREE``.