From 98d26bdd2c054d31cb17785e3192ccaa944972f9 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 26 Aug 2024 10:55:01 +1200
Subject: [PATCH] Docs: Fix nested list on build_verific page

---
 .../yosys_internals/extending_yosys/build_verific.rst       | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index b20517bd3..2585ebae4 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -81,8 +81,10 @@ The following features, along with their corresponding Yosys build parameters,
 are required for the Yosys-Verific patch:
 
 * RTL elaboration with
-   * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
-   * VHDL support with ``ENABLE_VERIFIC_VHDL``.
+
+  * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
+  * VHDL support with ``ENABLE_VERIFIC_VHDL``.
+
 * Hierarchy tree support and static elaboration with
   ``ENABLE_VERIFIC_HIER_TREE``.