mirror of https://github.com/YosysHQ/yosys.git
Clean up pseudo-private member usage, superfluous `std::vector` instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
This commit is contained in:
Alberto Gonzalez
parent
283b1130a6
commit
985a29ff3b
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@ -54,8 +54,8 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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if (chunk.wire != NULL) {
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IdString wire_name = chunk.wire->name;
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apply_prefix(prefix, wire_name);
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log_assert(module->wires_.count(wire_name) > 0);
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chunk.wire = module->wires_[wire_name];
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log_assert(module->wire(wire_name) != nullptr);
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chunk.wire = module->wire(wire_name);
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}
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sig = chunks;
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}
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@ -132,8 +132,8 @@ struct TechmapWorker
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if (module == NULL)
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return result;
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for (auto &it : module->wires_) {
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const char *p = it.first.c_str();
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for (auto w : module->wires()) {
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const char *p = w->name.c_str();
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if (*p == '$')
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continue;
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@ -142,11 +142,11 @@ struct TechmapWorker
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if (!strncmp(p, "_TECHMAP_", 9)) {
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TechmapWireData record;
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record.wire = it.second;
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record.value = it.second;
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record.wire = w;
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record.value = w;
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result[p].push_back(record);
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it.second->attributes[ID::keep] = RTLIL::Const(1);
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it.second->attributes[ID::_techmap_special_] = RTLIL::Const(1);
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w->attributes[ID::keep] = RTLIL::Const(1);
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w->attributes[ID::_techmap_special_] = RTLIL::Const(1);
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}
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}
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@ -165,7 +165,7 @@ struct TechmapWorker
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if (tpl->processes.size() != 0) {
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log("Technology map yielded processes:");
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for (auto &it : tpl->processes)
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log(" %s",RTLIL::id2cstr(it.first));
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log(" %s",log_id(it.first));
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log("\n");
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if (autoproc_mode) {
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Pass::call_on_module(tpl->design, tpl, "proc");
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@ -179,8 +179,8 @@ struct TechmapWorker
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orig_cell_name = cell->name.str();
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if (!flatten_mode) {
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for (auto &it : tpl->cells_)
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if (it.first == ID::_TECHMAP_REPLACE_) {
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for (auto tpl_cell : tpl->cells())
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if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
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module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
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break;
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}
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@ -208,26 +208,26 @@ struct TechmapWorker
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dict<Wire*, IdString> temp_renamed_wires;
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pool<SigBit> autopurge_tpl_bits;
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for (auto &it : tpl->wires_)
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for (auto tpl_w : tpl->wires())
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{
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if (it.second->port_id > 0)
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if (tpl_w->port_id > 0)
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{
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IdString posportname = stringf("$%d", it.second->port_id);
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positional_ports[posportname] = it.first;
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IdString posportname = stringf("$%d", tpl_w->port_id);
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positional_ports[posportname] = tpl_w->name;
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if (!flatten_mode && it.second->get_bool_attribute(ID::techmap_autopurge) &&
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(!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
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if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
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(!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) &&
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(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
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{
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if (sigmaps.count(tpl) == 0)
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sigmaps[tpl].set(tpl);
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for (auto bit : sigmaps.at(tpl)(it.second))
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for (auto bit : sigmaps.at(tpl)(tpl_w))
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if (bit.wire != nullptr)
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autopurge_tpl_bits.insert(bit);
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}
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}
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IdString w_name = it.second->name;
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IdString w_name = tpl_w->name;
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apply_prefix(cell->name, w_name);
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RTLIL::Wire *w = module->wire(w_name);
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if (w != nullptr) {
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@ -237,30 +237,30 @@ struct TechmapWorker
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w = nullptr;
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} else {
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w->attributes.erase(ID::hierconn);
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if (GetSize(w) < GetSize(it.second)) {
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if (GetSize(w) < GetSize(tpl_w)) {
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log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
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log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
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w->width = GetSize(it.second);
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log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell));
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w->width = GetSize(tpl_w);
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}
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}
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}
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if (w == nullptr) {
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w = module->addWire(w_name, it.second);
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w = module->addWire(w_name, tpl_w);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (!flatten_mode)
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w->attributes.erase(ID::techmap_autopurge);
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if (it.second->get_bool_attribute(ID::_techmap_special_))
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if (tpl_w->get_bool_attribute(ID::_techmap_special_))
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w->attributes.clear();
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if (w->attributes.count(ID::src))
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w->add_strpool_attribute(ID::src, extra_src_attrs);
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}
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design->select(module, w);
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if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {
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IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
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Wire *replace_w = module->addWire(replace_name, it.second);
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if (tpl_w->name.begins_with("\\_TECHMAP_REPLACE_.")) {
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IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), tpl_w->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
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Wire *replace_w = module->addWire(replace_name, tpl_w);
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module->connect(replace_w, w);
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}
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}
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@ -268,9 +268,9 @@ struct TechmapWorker
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SigMap tpl_sigmap(tpl);
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pool<SigBit> tpl_written_bits;
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for (auto &it1 : tpl->cells_)
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for (auto &it2 : it1.second->connections_)
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if (it1.second->output(it2.first))
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for (auto tpl_cell : tpl->cells())
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for (auto &it2 : tpl_cell->connections_)
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if (tpl_cell->output(it2.first))
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for (auto bit : tpl_sigmap(it2.second))
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tpl_written_bits.insert(bit);
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for (auto &it1 : tpl->connections_)
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@ -285,7 +285,7 @@ struct TechmapWorker
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RTLIL::IdString portname = it.first;
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if (positional_ports.count(portname) > 0)
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portname = positional_ports.at(portname);
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if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
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if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
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if (portname.begins_with("$"))
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
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continue;
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@ -294,7 +294,7 @@ struct TechmapWorker
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if (GetSize(it.second) == 0)
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continue;
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RTLIL::Wire *w = tpl->wires_.at(portname);
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RTLIL::Wire *w = tpl->wire(portname);
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RTLIL::SigSig c, extra_connect;
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if (w->port_output && !w->port_input) {
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@ -377,19 +377,19 @@ struct TechmapWorker
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}
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}
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for (auto &it : tpl->cells_)
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for (auto tpl_cell : tpl->cells())
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{
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IdString c_name = it.second->name.str();
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IdString c_name = tpl_cell->name;
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bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
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if (techmap_replace_cell)
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c_name = orig_cell_name;
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else if (it.second->name.begins_with("\\_TECHMAP_REPLACE_."))
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else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_."))
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c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
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else
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apply_prefix(cell->name, c_name);
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RTLIL::Cell *c = module->addCell(c_name, it.second);
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RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
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design->select(module, c);
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if (!flatten_mode && c->type.begins_with("\\$"))
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@ -493,9 +493,9 @@ struct TechmapWorker
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std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
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std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
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for (auto cell : module->cells())
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for (auto cell : module->selected_cells())
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{
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if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
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if (handled_cells.count(cell) > 0)
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continue;
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std::string cell_type = cell->type.str();
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@ -511,7 +511,7 @@ struct TechmapWorker
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if (flatten_mode) {
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bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
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for (auto &tpl_name : celltypeMap.at(cell_type))
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if (map->modules_[tpl_name]->get_bool_attribute(ID::keep_hierarchy))
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if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy))
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keepit = true;
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if (keepit) {
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if (!flatten_keep_list[cell]) {
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@ -533,7 +533,7 @@ struct TechmapWorker
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continue;
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for (auto &tpl_name : celltypeMap.at(cell_type)) {
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RTLIL::Module *tpl = map->modules_[tpl_name];
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RTLIL::Module *tpl = map->module(tpl_name);
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RTLIL::Wire *port = tpl->wire(conn.first);
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if (port && port->port_input)
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cell_to_inbit[cell].insert(sig.begin(), sig.end());
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@ -567,7 +567,7 @@ struct TechmapWorker
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for (auto &tpl_name : celltypeMap.at(cell_type))
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{
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RTLIL::IdString derived_name = tpl_name;
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RTLIL::Module *tpl = map->modules_[tpl_name];
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RTLIL::Module *tpl = map->module(tpl_name);
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std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
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if (tpl->get_blackbox_attribute(ignore_wb))
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@ -675,7 +675,7 @@ struct TechmapWorker
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if (extmapper_name == "simplemap") {
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if (simplemap_mappers.count(cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
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log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
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simplemap_mappers.at(cell->type)(module, cell);
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}
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@ -697,7 +697,7 @@ struct TechmapWorker
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for (auto conn : cell->connections()) {
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if (conn.first.begins_with("$"))
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continue;
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if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
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if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
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continue;
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if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
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goto next_tpl;
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@ -713,20 +713,20 @@ struct TechmapWorker
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parameters[ID::_TECHMAP_CELLTYPE_] = RTLIL::unescape_id(cell->type);
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for (auto conn : cell->connections()) {
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
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std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
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for (auto &bit : v)
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bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
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parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
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parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))] = RTLIL::SigSpec(v).as_const();
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}
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
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std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
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for (auto &bit : v)
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if (bit.wire != NULL)
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bit = RTLIL::SigBit(RTLIL::State::Sx);
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parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
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parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))] = RTLIL::SigSpec(v).as_const();
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}
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
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auto sig = sigmap(conn.second);
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RTLIL::Const value(State::Sx, sig.size());
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for (int i = 0; i < sig.size(); i++) {
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@ -735,7 +735,7 @@ struct TechmapWorker
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value[i] = it->second;
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}
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}
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parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
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parameters[stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))] = value;
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}
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}
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@ -747,8 +747,8 @@ struct TechmapWorker
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unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
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for (auto conn : cell->connections())
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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for (auto &bit : sigmap(conn.second).to_sigbit_vector())
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
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for (auto &bit : sigmap(conn.second))
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if (unique_bit_id.count(bit) == 0)
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unique_bit_id[bit] = unique_bit_id_counter++;
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}
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@ -764,13 +764,13 @@ struct TechmapWorker
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parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
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for (auto conn : cell->connections())
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
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RTLIL::Const value;
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for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
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for (auto &bit : sigmap(conn.second)) {
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RTLIL::Const chunk(unique_bit_id.at(bit), bits);
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value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
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}
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parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
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parameters[stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))] = value;
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}
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}
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@ -819,7 +819,7 @@ struct TechmapWorker
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RTLIL::SigSpec value = it.value;
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if (value.is_fully_const() && value.as_bool()) {
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log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
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derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
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derived_name.c_str(), log_id(it.wire->name), log_signal(value));
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techmap_do_cache[tpl] = false;
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}
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}
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@ -835,7 +835,7 @@ struct TechmapWorker
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auto &data = it.second.front();
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if (!data.value.is_fully_const())
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log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
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log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value));
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techmap_wire_names.erase(it.first);
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@ -926,7 +926,7 @@ struct TechmapWorker
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log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
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std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
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while (tpl->wires_.count(new_name))
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while (tpl->wire(new_name) != nullptr)
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new_name += "_";
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tpl->rename(data.wire->name, new_name);
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@ -942,12 +942,12 @@ struct TechmapWorker
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if (techmap_do_cache[tpl])
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for (auto &it2 : it.second)
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if (!it2.value.is_fully_const())
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log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
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log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value));
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techmap_wire_names.erase(it.first);
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}
|
||||
|
||||
for (auto &it : techmap_wire_names)
|
||||
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
|
||||
log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", log_id(it));
|
||||
|
||||
if (recursive_mode) {
|
||||
if (log_continue) {
|
||||
|
|
@ -1301,17 +1301,16 @@ struct TechmapPass : public Pass {
|
|||
log_header(design, "Continuing TECHMAP pass.\n");
|
||||
|
||||
std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
|
||||
for (auto &it : map->modules_) {
|
||||
if (it.second->attributes.count(ID::techmap_celltype) && !it.second->attributes.at(ID::techmap_celltype).bits.empty()) {
|
||||
char *p = strdup(it.second->attributes.at(ID::techmap_celltype).decode_string().c_str());
|
||||
for (auto module : map->modules()) {
|
||||
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
|
||||
char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
|
||||
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
|
||||
celltypeMap[RTLIL::escape_id(q)].insert(it.first);
|
||||
celltypeMap[RTLIL::escape_id(q)].insert(module->name);
|
||||
free(p);
|
||||
} else {
|
||||
string module_name = it.first.str();
|
||||
if (it.first.begins_with("\\$"))
|
||||
module_name = module_name.substr(1);
|
||||
celltypeMap[module_name].insert(it.first);
|
||||
std::string module_name = module->name.begins_with("\\$") ?
|
||||
module->name.substr(1) : module->name.str();
|
||||
celltypeMap[module_name].insert(module->name);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1402,10 +1401,9 @@ struct FlattenPass : public Pass {
|
|||
worker.flatten_do_list.erase(mod->name);
|
||||
}
|
||||
} else {
|
||||
for (auto mod : vector<Module*>(design->modules())) {
|
||||
for (auto mod : design->modules().to_vector())
|
||||
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
|
||||
}
|
||||
}
|
||||
|
||||
log_suppressed();
|
||||
log("No more expansions possible.\n");
|
||||
|
|
@ -1425,15 +1423,11 @@ struct FlattenPass : public Pass {
|
|||
new_used_modules.insert(cell->type);
|
||||
}
|
||||
|
||||
dict<RTLIL::IdString, RTLIL::Module*> new_modules;
|
||||
for (auto mod : vector<Module*>(design->modules()))
|
||||
if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
|
||||
new_modules[mod->name] = mod;
|
||||
} else {
|
||||
for (auto mod : design->modules())
|
||||
if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
|
||||
log("Deleting now unused module %s.\n", log_id(mod));
|
||||
delete mod;
|
||||
design->remove(mod);
|
||||
}
|
||||
design->modules_.swap(new_modules);
|
||||
}
|
||||
|
||||
log_pop();
|
||||
|
|
|
|||
Loading…
Reference in New Issue