mirror of https://github.com/YosysHQ/yosys.git
Use feedback path for MACC
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a09e69dd56
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@ -51,21 +51,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell));
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bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell));
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SigSpec P = st.sigP;
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SigSpec P = st.sigP;
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if (st.addAB) {
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log_assert(st.addAB->getParam("\\A_SIGNED").as_bool());
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log_assert(st.addAB->getParam("\\B_SIGNED").as_bool());
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log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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SigSpec C = st.sigC;
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C.extend_u0(48, true);
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cell->setPort("\\C", C);
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SigSpec &opmode = cell->connections_.at("\\OPMODE");
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opmode[6] = State::S0;
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opmode[5] = State::S1;
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opmode[4] = State::S1;
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pm.autoremove(st.addAB);
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}
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if (st.clock != SigBit())
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if (st.clock != SigBit())
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{
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{
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cell->setPort("\\CLK", st.clock);
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cell->setPort("\\CLK", st.clock);
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@ -140,6 +125,27 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("\n");
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log("\n");
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}
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}
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if (st.addAB) {
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log_assert(st.addAB->getParam("\\A_SIGNED").as_bool());
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log_assert(st.addAB->getParam("\\B_SIGNED").as_bool());
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log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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SigSpec C = st.sigC;
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SigSpec &opmode = cell->connections_.at("\\OPMODE");
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if (cell->getParam("\\PREG").as_bool() && C == P) {
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opmode[4] = State::S0;
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}
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else {
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C.extend_u0(48, true);
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cell->setPort("\\C", C);
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opmode[4] = State::S1;
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}
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opmode[6] = State::S0;
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opmode[5] = State::S1;
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pm.autoremove(st.addAB);
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}
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if (GetSize(P) < 48)
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if (GetSize(P) < 48)
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P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
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P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
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cell->setPort("\\P", P);
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cell->setPort("\\P", P);
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