mirror of https://github.com/YosysHQ/yosys.git
Fixed use of frozen literals in SatGen
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8406e7f7b6
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97710ffad5
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@ -66,13 +66,12 @@ struct SatGen
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if (c.wire == NULL) {
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RTLIL::State bit = c.data.bits.at(0);
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if (model_undef && dup_undef && bit == RTLIL::State::Sx)
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vec.push_back(ez->literal());
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vec.push_back(ez->frozen_literal());
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else
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vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->TRUE : ez->FALSE);
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} else {
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std::string name = pf + stringf(c.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset);
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vec.push_back(ez->literal(name));
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ez->freeze(vec.back());
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vec.push_back(ez->frozen_literal(name));
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}
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return vec;
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}
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