mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #322 from azonenberg/master
Add POUT to GP_COUNTx cells
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commit
931d775b0b
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@ -53,7 +53,7 @@ module GP_CLKBUF(input wire IN, output wire OUT);
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assign OUT = IN;
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assign OUT = IN;
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endmodule
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endmodule
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module GP_COUNT8(input CLK, input wire RST, output reg OUT);
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module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_MODE = "RISING";
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@ -67,6 +67,7 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT);
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//Combinatorially output whenever we wrap low
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//Combinatorially output whenever we wrap low
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always @(*) begin
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always @(*) begin
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OUT <= (count == 8'h0);
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OUT <= (count == 8'h0);
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OUT <= count;
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end
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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@ -103,7 +104,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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endmodule
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endmodule
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module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP);
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter RESET_VALUE = "ZERO";
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@ -116,7 +117,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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endmodule
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endmodule
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module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP);
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter RESET_VALUE = "ZERO";
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