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quicklogic: Testing split TDP36K 

Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
This commit is contained in:
Krystine Sherwin 2023-11-29 17:34:22 +13:00 committed by Martin Povišer
parent 991850e1c9
commit 8d3b238b9b
2 changed files with 93 additions and 30 deletions
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40
tests/arch/common/blockram.v
View File

@ -96,6 +96,46 @@ module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra
endmodule // sync_ram_sdp_wrr endmodule // sync_ram_sdp_wrr
module double_sync_ram_sdp #(parameter DATA_WIDTH_A=8, ADDRESS_WIDTH_A=10, DATA_WIDTH_B=8, ADDRESS_WIDTH_B=10)
(
input wire write_enable_a, clk_a,
input wire [DATA_WIDTH_A-1:0] data_in_a,
input wire [ADDRESS_WIDTH_A-1:0] address_in_r_a, address_in_w_a,
output wire [DATA_WIDTH_A-1:0] data_out_a,
input wire write_enable_b, clk_b,
input wire [DATA_WIDTH_B-1:0] data_in_b,
input wire [ADDRESS_WIDTH_B-1:0] address_in_r_b, address_in_w_b,
output wire [DATA_WIDTH_B-1:0] data_out_b
);
sync_ram_sdp #(
.DATA_WIDTH(DATA_WIDTH_A),
.ADDRESS_WIDTH(ADDRESS_WIDTH_A)
) a_ram (
.write_enable(write_enable_a),
.clk(clk_a),
.data_in(data_in_a),
.address_in_r(address_in_r_a),
.address_in_w(address_in_w_a),
.data_out(data_out_a)
);
sync_ram_sdp #(
.DATA_WIDTH(DATA_WIDTH_B),
.ADDRESS_WIDTH(ADDRESS_WIDTH_B)
) b_ram (
.write_enable(write_enable_b),
.clk(clk_b),
.data_in(data_in_b),
.address_in_r(address_in_r_b),
.address_in_w(address_in_w_b),
.data_out(data_out_b)
);
endmodule // double_sync_ram_sdp
module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
(input wire clk_a, clk_b, (input wire clk_a, clk_b,
input wire write_enable_a, write_enable_b, input wire write_enable_a, write_enable_b,

83
tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
View File

@ -1,51 +1,74 @@
blockram_template = """\ blockram_template = """# ======================================
design -reset; read_verilog -defer ../../common/blockram.v design -reset; read_verilog -defer ../../common/blockram.v
chparam -set ADDRESS_WIDTH {aw} -set DATA_WIDTH {dw} {top} chparam{param_str} {top}
hierarchy -top {top} hierarchy -top {top}
synth_quicklogic -family qlf_k6n10f -top {top}; cd {top} synth_quicklogic -family qlf_k6n10f -top {top}; cd {top}
log TESTING aw:{aw} dw:{dw} top:{top}\ log ** TESTING {top} WITH PARAMS{param_str}\
""" """
blockram_tests: "list[tuple[int, int, str, list[str]]]" = [ blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
# TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work
(10, 36, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
(11, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
(12, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
# larger sizes need an extra ram # larger sizes need an extra ram
(10, 48, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 48)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
(11, 36, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
(12, 18, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
(12, 10, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 10)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
# 4096x20bit *can* fit in 3, albeit somewhat awkwardly # 4096x20bit *can* fit in 3, albeit somewhat awkwardly
(12, 20, "sync_ram_*dp", ["-assert-min 3 t:TDP36K", ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_*dp", ["-assert-min 3 t:TDP36K",
"-assert-max 4 t:TDP36K"]), "-assert-max 4 t:TDP36K"]),
# smaller sizes can still fit in one
(10, 32, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), # smaller sizes can still fit in one, and assign the correct width (1, 2, 4, 8, 18 or 36)
(10, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]),
(10, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 24)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]),
(11, 16, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]),
(11, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
(12, 8, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]),
(13, 4, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
(14, 2, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
(15, 1, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 4)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=4 %i"]),
([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]),
([("ADDRESS_WIDTH", 15), ("DATA_WIDTH", 1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]),
# 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K) # 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K)
(11, 18, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
(11, 9, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
# 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K) # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K)
(11, 18, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
(10, 36, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
# two disjoint 18K memories can share a single TDP36K
([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),
("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16),
("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
([("ADDRESS_WIDTH_A", 14), ("DATA_WIDTH_A", 1),
("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
# but only if data width is <= 18
([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36),
("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]),
# sharing a TDP36K sets is_split=1
([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),
("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]),
# an unshared TDP36K sets is_split=0
([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]),
] ]
with open("t_mem.ys", mode="w") as f: with open("t_mem.ys", mode="w") as f:
for (aw, dw, top, assertions) in blockram_tests: for (params, top, assertions) in blockram_tests:
param_str = ""
for (key, val) in params:
param_str += f" -set {key} {val}"
if "*" in top: if "*" in top:
star_sub = ["s", "t"] star_sub = ["s", "t"]
else: else:
star_sub = [""] star_sub = [""]
for sub in star_sub: for sub in star_sub:
print( print(
blockram_template.format(aw=aw, dw=dw, top=top.replace("*", sub)), blockram_template.format(param_str=param_str, top=top.replace("*", sub)),
file=f file=f
) )
for assertion in assertions: for assertion in assertions:
print("select {}\n".format(assertion), file=f, end=None) print("select {}".format(assertion), file=f)
print("", file=f)